Searched refs:cycle (Results 1 – 11 of 11) sorted by relevance
32 unsigned int cycle; in stopwatch_set_usecs() local36 cycle = US_TO_CYCLE(usecs); in stopwatch_set_usecs()37 mmio_write_32(SYST_RVR, cycle); in stopwatch_set_usecs()
22 - A dedicated cycle counter: ``PMCCNTR``.47 configures it. The cycle counter has the ``PMCCFILTR_EL0`` register, which has127 - If set to ``1`` enables the cycle counter ``PMCCNTR``.134 - If set to ``1`` it disables the cycle counter ``PMCCNTR`` where event
102 The service captures the cycle count, which allows for the time spent in the
85 - ``SCCD`` for the cycle counter.92 - Prohibit general event counters and the cycle counter:109 - Prohibit cycle counter: ``MDCR_EL3.SPME == 0 && PMCR_EL0.DP == 1``.115 - Prohibit cycle counter: ``MDCR_EL3.SCCD == 1``
29 interface will be removed. This must be at least 1 full release cycle in future.
38 Rnote over RMM: Platform token is\n\ cached. It is not\n\ changing within\n\ a power cycle.
32 bit is set to zero, the cycle counter (when enabled) counts during secure world
24 - Focus on the run-time part of the life-cycle (no specific emphasis on boot
1033 | | | General events and cycle counting in the Secure |
1608 Trusted OS functionality. It is also useful to reduce jitter and cycle
3700 …- manage cards power cycle ([258bef9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trus…6798 resume, Update DDR setting rev.0.35, qos: change subslot cycle, Change6890 secure world entry/exit from/to Non-secure state, and cycle counting gets6896 cycle counting gets disabled by setting PMCR_EL0.DP bit.7748 - Control register PMCR_EL0 / PMCR is set to prohibit cycle counting in the
