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Searched refs:cs (Results 1 – 25 of 27) sorted by relevance

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/trusted-firmware-a-latest/plat/marvell/armada/common/
Dmarvell_ddr_info.c15 #define DRAM_CH0_MMAP_LOW_REG(iface, cs, base) \ argument
16 (base + DRAM_CH0_MMAP_LOW_OFFSET + (iface) * 0x10000 + (cs) * 0x8)
17 #define DRAM_CH0_MMAP_HIGH_REG(iface, cs, base) \ argument
18 (DRAM_CH0_MMAP_LOW_REG(iface, cs, base) + 4)
29 #define DRAM_CS_ENABLED(iface, cs, base) \ argument
30 (mmio_read_32(DRAM_CH0_MMAP_LOW_REG(iface, cs, base)) & \
32 #define GET_DRAM_REGION_SIZE_CODE(iface, cs, base) \ argument
33 (mmio_read_32(DRAM_CH0_MMAP_LOW_REG(iface, cs, base)) & \
81 uint8_t cs, iface; in mvebu_get_dram_size() local
84 for (cs = 0; cs < DRAM_MAX_CS_NUM; cs++) { in mvebu_get_dram_size()
[all …]
/trusted-firmware-a-latest/plat/nxp/soc-lx2160a/lx2160aqds/
Dddr_init.c27 .cs[0].bnds = U(0x03FF),
28 .cs[1].bnds = U(0x03FF),
29 .cs[0].config = U(0x80050422),
30 .cs[1].config = U(0x80000422),
31 .cs[2].bnds = U(0x00),
32 .cs[3].bnds = U(0x00),
33 .cs[2].config = U(0x00),
34 .cs[3].config = U(0x00),
78 .cs[0].bnds = U(0x03FF),
79 .cs[1].bnds = U(0x03FF),
[all …]
/trusted-firmware-a-latest/plat/nxp/soc-lx2160a/lx2162aqds/
Dddr_init.c27 .cs[0].bnds = U(0x03FFU),
28 .cs[1].bnds = U(0x03FF),
29 .cs[0].config = U(0x80050422),
30 .cs[1].config = U(0x80000422),
31 .cs[2].bnds = U(0x00),
32 .cs[3].bnds = U(0x00),
33 .cs[2].config = U(0x00),
34 .cs[3].config = U(0x00),
78 .cs[0].bnds = U(0x03FF),
79 .cs[1].bnds = U(0x03FF),
[all …]
/trusted-firmware-a-latest/plat/nxp/soc-ls1046a/ls1046ardb/
Dddr_init.c20 .cs[0].config = U(0x80040322),
21 .cs[0].bnds = U(0x1FF),
22 .cs[1].config = U(0x80000322),
23 .cs[1].bnds = U(0x1FF),
65 .cs[0].config = U(0x80040322),
66 .cs[0].bnds = U(0x1FF),
67 .cs[1].config = U(0x80000322),
68 .cs[1].bnds = U(0x1FF),
110 .cs[0].config = U(0x80040322),
111 .cs[0].bnds = U(0x1FF),
[all …]
/trusted-firmware-a-latest/drivers/renesas/common/ddr/ddr_b/
Dboot_init_dram.c2345 uint32_t ch, cs; in dbsc_regset_post() local
2352 for (cs = 0; cs < CS_CNT; cs++) { in dbsc_regset_post()
2353 if ((ch_have_this_cs[cs] & (1U << ch)) != 0) { in dbsc_regset_post()
2357 cs); in dbsc_regset_post()
2395 for (cs = 0; cs < CS_CNT; cs++) { in dbsc_regset_post()
2396 if (ddr_density[ch][cs] == 0xff) { in dbsc_regset_post()
2397 mmio_write_32(DBSC_DBMEMCONF(ch, cs), 0x00); in dbsc_regset_post()
2399 mmio_write_32(DBSC_DBMEMCONF(ch, cs), in dbsc_regset_post()
2401 [cs])); in dbsc_regset_post()
3268 uint32_t cs, slice; in wdqdm_clr1() local
[all …]
Dboot_init_dram_regdef.h31 #define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs))) argument
/trusted-firmware-a-latest/lib/transfer_list/
Dtransfer_list.c226 uint8_t cs = 0; in calc_byte_sum() local
234 cs += b[n]; in calc_byte_sum()
237 return cs; in calc_byte_sum()
246 uint8_t cs; in transfer_list_update_checksum() local
252 cs = calc_byte_sum(tl); in transfer_list_update_checksum()
253 cs -= tl->checksum; in transfer_list_update_checksum()
254 cs = 256 - cs; in transfer_list_update_checksum()
255 tl->checksum = cs; in transfer_list_update_checksum()
/trusted-firmware-a-latest/drivers/nxp/ddr/nxp-ddr/
Dddrc.c196 const int mod_bnds = regs->cs[0].config & CTLR_INTLV_MASK; in ddrc_set_regs()
221 (regs->cs[i].bnds & U(0xfffefffe)) >> 1U); in ddrc_set_regs()
223 ddr_out32(&ddr->bnds[i].a, regs->cs[i].bnds); in ddrc_set_regs()
225 ddr_out32(&ddr->csn_cfg_2[i], regs->cs[i].config_2); in ddrc_set_regs()
405 (regs->cs[i].config & ~CTLR_INTLV_MASK)); in ddrc_set_regs()
407 ddr_out32(&ddr->csn_cfg[i], regs->cs[i].config); in ddrc_set_regs()
456 if ((regs->cs[i].config & 0x80000000) == 0) { in ddrc_set_regs()
460 ((regs->cs[i].config >> 14) & 0x3) + 2 + in ddrc_set_regs()
461 ((regs->cs[i].config >> 8) & 0x7) + 12 + in ddrc_set_regs()
462 ((regs->cs[i].config >> 4) & 0x3) + 0 + in ddrc_set_regs()
[all …]
Dregs.c59 regs->cs[i].config = ((cs_n_en & 0x1) << 31) | in cal_csn_config()
70 debug(" _config = 0x%x\n", regs->cs[i].config); in cal_csn_config()
736 ((regs->cs[i].config & SDRAM_CS_CONFIG_EN) != 0)) { in cal_ddr_sdram_mode()
903 regs->cs[i].bnds = ((sa & 0xffff) << 16) | in cal_ddr_csn_bnds()
908 regs->cs[i].bnds = 0xffffffff; in cal_ddr_csn_bnds()
911 debug("cs[%d].bnds = 0x%x\n", i, regs->cs[i].bnds); in cal_ddr_csn_bnds()
920 const unsigned int cs0_config = regs->cs[0].config; in cal_ddr_addr_dec()
925 unsigned int cs; in cal_ddr_addr_dec() local
953 cs = 1; in cal_ddr_addr_dec()
956 cs = 2; in cal_ddr_addr_dec()
[all …]
/trusted-firmware-a-latest/lib/debugfs/
Ddevfip.c191 chan_t cs; in fipread() local
208 if (clone(fip->c, &cs) == NULL) { in fipread()
226 if (devtab[cs.index]->seek(&cs, off, KSEEK_SET) < 0) { in fipread()
230 n = devtab[cs.index]->read(&cs, buf, n); in fipread()
/trusted-firmware-a-latest/plat/nxp/soc-lx2160a/lx2160ardb/
Dddr_init.c26 .cs[0].config = U(0xA8050322),
27 .cs[1].config = U(0x80000322),
28 .cs[0].bnds = U(0x3FF),
29 .cs[1].bnds = U(0x3FF),
/trusted-firmware-a-latest/drivers/mtd/spi-mem/
Dspi_mem.c27 unsigned int cs; member
164 ret = ops->claim_bus(spi_slave.cs); in spi_mem_exec_op()
217 spi_slave.cs = fdt32_to_cpu(*cuint); in spi_mem_init_slave()
/trusted-firmware-a-latest/plat/nxp/soc-ls1043a/ls1043ardb/
Dddr_init.c18 .cs[0].config = U(0x80040322),
19 .cs[0].bnds = U(0x7F),
/trusted-firmware-a-latest/include/drivers/
Dspi_mem.h94 int (*claim_bus)(unsigned int cs);
/trusted-firmware-a-latest/plat/nxp/soc-ls1046a/ls1046afrwy/
Dddr_init.c20 .cs[0].config = U(0x80010412),
21 .cs[0].bnds = U(0x7F),
/trusted-firmware-a-latest/drivers/brcm/spi/
Diproc_qspi.h100 int iproc_qspi_setup(uint32_t bus, uint32_t cs,
Diproc_qspi.c29 int iproc_qspi_setup(uint32_t bus, uint32_t cs, uint32_t max_hz, uint32_t mode) in iproc_qspi_setup() argument
/trusted-firmware-a-latest/plat/nxp/soc-ls1028a/ls1028ardb/
Dddr_init.c16 .cs[0].config = U(0x80040422),
17 .cs[0].bnds = U(0xFF),
/trusted-firmware-a-latest/drivers/renesas/common/
Dddr_regs.h16 #define DBSC_DBMEMCONF(ch, cs) (0xE6790030U + 0x10U * (ch) + 0x04U * (cs)) argument
/trusted-firmware-a-latest/drivers/st/fmc/
Dstm32_fmc2_nand.c149 struct stm32_fmc2_cs_reg cs[MAX_CS]; member
570 uintptr_t data_base = stm32_fmc2.cs[stm32_fmc2.cs_sel].data_base; in stm32_fmc2_read_data()
617 uintptr_t data_base = stm32_fmc2.cs[stm32_fmc2.cs_sel].data_base; in stm32_fmc2_write_data()
707 mmio_write_8(stm32_fmc2.cs[stm32_fmc2.cs_sel].cmd_base, in stm32_fmc2_exec()
712 mmio_write_8(stm32_fmc2.cs[stm32_fmc2.cs_sel].addr_base, in stm32_fmc2_exec()
865 stm32_fmc2.cs[i].data_base = fdt32_to_cpu(*(cuint + 1)) + in stm32_fmc2_init()
872 stm32_fmc2.cs[i].cmd_base = fdt32_to_cpu(*(cuint + 4)) + in stm32_fmc2_init()
879 stm32_fmc2.cs[i].addr_base = fdt32_to_cpu(*(cuint + 7)) + in stm32_fmc2_init()
/trusted-firmware-a-latest/include/drivers/nxp/ddr/
Dddr.h54 } cs[MAX_CS_NUM]; member
/trusted-firmware-a-latest/drivers/st/spi/
Dstm32_qspi.c337 static int stm32_qspi_claim_bus(unsigned int cs) in stm32_qspi_claim_bus() argument
341 if (cs >= QSPI_MAX_CHIP) { in stm32_qspi_claim_bus()
347 if (cs == 1U) { in stm32_qspi_claim_bus()
/trusted-firmware-a-latest/plat/intel/soc/common/drivers/qspi/
Dcadence_qspi.c100 int cad_qspi_stig_cmd_helper(int cs, uint32_t cmd) in cad_qspi_stig_cmd_helper() argument
107 & CAD_QSPI_CFG_CS_MSK) | CAD_QSPI_CFG_CS(cs)); in cad_qspi_stig_cmd_helper()
501 void cad_qspi_set_chip_select(int cs) in cad_qspi_set_chip_select() argument
503 cad_qspi_cs = cs; in cad_qspi_set_chip_select()
Dcadence_qspi.h167 void cad_qspi_set_chip_select(int cs);
/trusted-firmware-a-latest/plat/rockchip/rk3399/drivers/dram/
Ddram_spec_timing.c130 uint32_t cs, ch; in get_max_die_capability() local
133 for (cs = 0; cs < timing_config->dram_info[ch].cs_cnt; cs++) { in get_max_die_capability()
136 dram_info[ch].per_die_capability[cs]); in get_max_die_capability()

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