| /trusted-firmware-a-latest/include/lib/extensions/ |
| D | sme.h | 26 void sme_enable(cpu_context_t *context);
27 void sme_disable(cpu_context_t *context);
37 static inline void sme_enable(cpu_context_t *context) in sme_enable() argument
40 static inline void sme_disable(cpu_context_t *context) in sme_disable() argument
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| D | mpam.h | 15 void mpam_enable(cpu_context_t *context);
18 static inline void mpam_enable(cpu_context_t *context) in mpam_enable() argument
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| /trusted-firmware-a-latest/bl31/ |
| D | bl31_context_mgmt.c | 31 void cm_set_context(void *context, uint32_t security_state) in cm_set_context() argument
36 context); in cm_set_context()
58 void cm_set_context_by_index(unsigned int cpu_idx, void *context, in cm_set_context_by_index() argument
65 context); in cm_set_context_by_index()
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| /trusted-firmware-a-latest/include/lib/el3_runtime/ |
| D | context_mgmt.h | 28 void *context,
31 void cm_set_context(void *context, uint32_t security_state);
67 static inline void cm_set_next_context(void *context) in cm_set_next_context() argument
85 : : "r" (context)); in cm_set_next_context()
90 void cm_set_next_context(void *context);
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| /trusted-firmware-a-latest/lib/extensions/mpam/ |
| D | mpam.c | 14 void mpam_enable(cpu_context_t *context) in mpam_enable() argument
18 mpam3_el3 = read_ctx_reg(get_el3state_ctx(context), CTX_MPAM3_EL3); in mpam_enable()
26 write_ctx_reg(get_el3state_ctx(context), CTX_MPAM3_EL3, mpam3_el3); in mpam_enable()
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| /trusted-firmware-a-latest/lib/extensions/sme/ |
| D | sme.c | 17 void sme_enable(cpu_context_t *context) in sme_enable() argument
23 state = get_el3state_ctx(context); in sme_enable()
87 void sme_disable(cpu_context_t *context) in sme_disable() argument
93 state = get_el3state_ctx(context); in sme_disable()
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| /trusted-firmware-a-latest/docs/design_documents/ |
| D | context_mgmt_rework.rst | 13 The context management library in TF-A provides the basic CPU context
30 The below section lays down the design principles for re-factoring the context
33 (1) **Decentralized model for context mgmt**
37 dispatcher to own the context for their respective world and moving away
38 from a centralized policy management by context management library will
44 firmware (BL31)/context management library needs to have routines to help
45 initialize the Non Secure world context.
59 (3) **Maintain EL3 sysregs which affect lower EL within CPU context**
61 The CPU context contains some EL3 sysregs and gets applied on a per-world
62 basis (eg: cptr_el3, scr_el3, zcr_el3 is part of the context
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| /trusted-firmware-a-latest/drivers/nxp/crypto/caam/src/auth/ |
| D | hash.c | 64 int hash_update(enum hash_algo algo, void *context, void *data_ptr, in hash_update() argument
67 struct hash_ctx *ctx = context; in hash_update()
111 int hash_final(enum hash_algo algo, void *context, void *hash_ptr, in hash_final() argument
115 struct hash_ctx *ctx = context; in hash_final()
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| /trusted-firmware-a-latest/bl32/sp_min/ |
| D | sp_min_main.c | 79 void cm_set_context(void *context, uint32_t security_state) in cm_set_context() argument
82 sp_min_cpu_ctx_ptr[plat_my_core_pos()] = context; in cm_set_context()
102 void cm_set_context_by_index(unsigned int cpu_idx, void *context, in cm_set_context_by_index() argument
106 sp_min_cpu_ctx_ptr[cpu_idx] = context; in cm_set_context_by_index()
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| /trusted-firmware-a-latest/include/drivers/nxp/crypto/caam/ |
| D | hash.h | 80 int hash_update(enum hash_algo algo, void *context, void *data_ptr,
82 int hash_final(enum hash_algo algo, void *context, void *hash_ptr,
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| /trusted-firmware-a-latest/docs/security_advisories/ |
| D | security-advisory-tfv-8.rst | 26 When taking an exception to EL3, BL31 saves the CPU context. The aim is to
29 ``x0`` to ``x3`` are not part of the CPU context saved on the stack.
33 into the CPU context, typically using one of the ``SMC_RETx()`` macros provided
38 CPU context stored on the stack. This includes registers ``x0`` to ``x3``, as
39 can be seen in the ``lib/el3_runtime/aarch64/context.S`` file at line 339
46 * CPU context. x30 register must be explicitly restored by the caller.
53 remaining ones are left unchanged in the CPU context. As a result,
67 For this reason, TF-A does not save ``x0`` to ``x3`` in the CPU context on an
90 * spsr, lr, sp registers and the `scr` register to the SMC context on entry
97 /* Save r0 - r12 in the SMC context */
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| D | security-advisory-tfv-10.rst | 46 different context than seen in upstream code. Details of such context is
125 in ``auth_nvctr()`` - but neither of these can be exploited in the context of
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| D | security-advisory-tfv-5.rst | 45 sensible default values in the secure context.
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| /trusted-firmware-a-latest/bl1/aarch32/ |
| D | bl1_context_mgmt.c | 56 void cm_set_next_context(void *context) in cm_set_next_context() argument
58 assert(context != NULL); in cm_set_next_context()
59 bl1_next_cpu_context_ptr = context; in cm_set_next_context()
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| /trusted-firmware-a-latest/bl1/aarch64/ |
| D | bl1_context_mgmt.c | 28 void cm_set_context(void *context, uint32_t security_state) in cm_set_context() argument
31 bl1_cpu_context_ptr[security_state] = context; in cm_set_context()
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| /trusted-firmware-a-latest/docs/getting_started/ |
| D | psci-lib-integration-guide.rst | 37 context.
41 context and exiting to non-secure world. If the EL3 Runtime Software needs
42 additional configuration to be set for non-secure context, like routing
44 to programming. See `PSCI CPU context management`_ for more
45 details on CPU context management.
56 initializes/restores the non-secure CPU context as well.
63 #. On receipt of an SMC, save the register context as per `SMCCC`_.
73 PSCI CPU context management
84 The EL3 Runtime Software is responsible for managing register context
85 during switch between Normal and Secure worlds. The register context to be
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| D | build-internals.rst | 10 - ``CTX_INCLUDE_EL2_REGS``: This boolean option provides context save/restore
11 operations when entering/exiting an EL2 execution context. This is of primary
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| /trusted-firmware-a-latest/docs/components/ |
| D | xlat-tables-lib-v2-design.rst | 130 context* constitutes the superset of information used by the library to track
133 The library internally allocates a default translation context, which pertains
137 the default translation context or on an alternative one.
139 To register a translation context, the user must provide the library with the
144 The resulting translation context variable will be called after this name, to
146 ``foo``, the context variable name will be ``foo_xlat_ctx``.
154 Number of translation tables to statically allocate for this context,
158 for this context.
162 Size in bytes of the virtual address space to map using this context. This
169 Size in bytes of the physical address space to map using this context.
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| D | secure-partition-manager.rst | 153 ``SPMD_SPM_AT_SEL2`` is enabled. The context save/restore routine
573 - Pinned MP SPs: an execution context matches a physical PE. MP SPs must
575 - Migratable UP SPs: a single execution context can run and be migrated on any
578 the single execution context.
683 execution context. If the primary boot physical core linear id is N, an MP SP is
716 - Other SPs have their first execution context initialized as a result of secure
765 a specific execution context, as determined by the sender.
999 from its first execution context, to provide the entry point address for
1149 configuration is made part of a vCPU context.
1157 An SP execution context is said to be in SPMC scheduled mode if CPU cycles are
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| /trusted-firmware-a-latest/bl1/ |
| D | bl1.mk | 21 lib/el3_runtime/aarch64/context.S
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| /trusted-firmware-a-latest/lib/psci/ |
| D | psci_lib.mk | 24 PSCI_LIB_SOURCES += lib/el3_runtime/aarch64/context.S \
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| /trusted-firmware-a-latest/tools/conventional-changelog-tf-a/ |
| D | index.js | 168 writerOpts.transform = function (commit, context) { argument
193 return ccWriterOptsTransform(commit, context);
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| /trusted-firmware-a-latest/docs/design/ |
| D | interrupt-framework-design.rst | 37 context. It is always handled in Secure-EL1.
41 current execution context. It is always handled in either Non-secure EL1
45 depending upon the security state of the current execution context. It is
195 For example, in Arm GICv3, when the execution context is Secure-EL1/
341 via the context management library APIs.
342 A portable interrupt handler implementation must set the target context both in
343 the structure pointed to by the returned pointer and via the context management
371 context management library maintains a copy of the ``SCR_EL3`` system register for
634 #. Saving the entire general purpose register context (x0-x30) immediately
680 function is responsible for restoring the register context from the
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| /trusted-firmware-a-latest/docs/threat_model/ |
| D | threat_model_arm_cca.rst | 138 The following table analyses the :ref:`General Threats` in the context of this
176 The following table analyses the :ref:`Boot Firmware Threats` in the context of
198 The following table analyses the :ref:`Runtime Firmware Threats` in the context
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| D | threat_model_rss_interface.rst | 51 - ID 13: Relevant in the context of the realm attestation key, which can be
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