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Searched refs:clocks (Results 1 – 24 of 24) sorted by relevance

/trusted-firmware-a-latest/fdts/
Dstm32mp131.dtsi22 clocks = <&rcc CK_MPU>;
29 clocks {
85 clocks = <&rcc USART3_K>;
94 clocks = <&rcc UART4_K>;
103 clocks = <&rcc UART5_K>;
112 clocks = <&rcc UART7_K>;
121 clocks = <&rcc UART8_K>;
130 clocks = <&rcc USART6_K>;
138 clocks = <&rcc USBO_K>;
155 clocks = <&rcc USART1_K>;
[all …]
Dstm32mp151.dtsi40 clocks {
84 clocks = <&rcc TIM12_K>;
93 clocks = <&rcc USART2_K>;
102 clocks = <&rcc USART3_K>;
111 clocks = <&rcc UART4_K>;
121 clocks = <&rcc UART5_K>;
132 clocks = <&rcc I2C2_K>;
145 clocks = <&rcc UART7_K>;
154 clocks = <&rcc UART8_K>;
163 clocks = <&rcc USART6_K>;
[all …]
Dmorello-coresight.dtsi19 clocks = <&soc_refclk50mhz>;
27 clocks = <&soc_refclk50mhz>;
42 clocks = <&soc_refclk50mhz>;
50 clocks = <&soc_refclk50mhz>;
65 clocks = <&soc_refclk50mhz>;
73 clocks = <&soc_refclk50mhz>;
88 clocks = <&soc_refclk50mhz>;
96 clocks = <&soc_refclk50mhz>;
164 clocks = <&soc_refclk50mhz>;
178 clocks = <&soc_refclk50mhz>;
[all …]
Drtsm_ve-motherboard.dtsi127 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
131 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
139 clocks = <&v2m_clk24mhz>;
151 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
159 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
167 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
175 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
183 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
191 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
199 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
[all …]
Dstm32mp251.dtsi27 clocks {
96 clocks = <&rcc CK_KER_USART2>;
152 clocks = <&rcc CK_BUS_GPIOA>;
163 clocks = <&rcc CK_BUS_GPIOB>;
174 clocks = <&rcc CK_BUS_GPIOC>;
185 clocks = <&rcc CK_BUS_GPIOD>;
196 clocks = <&rcc CK_BUS_GPIOE>;
207 clocks = <&rcc CK_BUS_GPIOF>;
218 clocks = <&rcc CK_BUS_GPIOG>;
229 clocks = <&rcc CK_BUS_GPIOH>;
[all …]
Dfvp-foundation-motherboard.dtsi57 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
67 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
75 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
83 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
91 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
99 clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
107 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
115 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
123 clocks = <&v2m_clk24mhz>;
Dtc.dts111 clocks = <&scmi_dvfs 0>;
123 clocks = <&scmi_dvfs 0>;
135 clocks = <&scmi_dvfs 0>;
147 clocks = <&scmi_dvfs 0>;
159 clocks = <&scmi_dvfs 1>;
171 clocks = <&scmi_dvfs 1>;
183 clocks = <&scmi_dvfs 1>;
195 clocks = <&scmi_dvfs 2>;
244 clocks = <&soc_refclk100mhz>;
256 clocks = <&soc_refclk100mhz>;
[all …]
Dstm32mp13xc.dtsi14 clocks = <&rcc SAES_K>;
22 clocks = <&rcc PKA>;
Dstm32mp13xf.dtsi13 clocks = <&rcc SAES_K>;
21 clocks = <&rcc PKA>;
Dmorello-fvp.dts81 clocks = <&scmi_dvfs 0>;
89 clocks = <&scmi_dvfs 0>;
97 clocks = <&scmi_dvfs 1>;
105 clocks = <&scmi_dvfs 1>;
157 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
165 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
Dcorstone700.dtsi78 clocks = <&uartclk>, <&refclk100mhz>;
87 clocks = <&uartclk>, <&refclk100mhz>;
117 clocks = <&refclk100mhz>;
129 clocks = <&refclk100mhz>;
141 clocks = <&refclk100mhz>;
Dmorello-soc.dts63 clocks = <&scmi_dvfs 0>;
80 clocks = <&scmi_dvfs 0>;
97 clocks = <&scmi_dvfs 1>;
114 clocks = <&scmi_dvfs 1>;
230 clocks = <&dpu_aclk>;
237 clocks = <&scmi_clk 1>;
261 clocks = <&dpu_aclk>;
296 clocks = <&clk_gpu>;
430 clocks = <&soc_refclk85mhz>, <&i2s_audclk>, <&soc_refclk85mhz>;
440 clocks = <&i2s_audclk>;
Dstm32mp153.dtsi15 clocks = <&rcc CK_MPU>;
Dstm32mp15xc.dtsi13 clocks = <&rcc CRYP1>;
Da5ds.dts92 clocks = <&refclk24mhz>;
112 clocks = <&refclk7500khz>;
121 clocks = <&refclk7500khz>;
Dn1sdp-single-chip.dts51 clocks = <&soc_hdlcdclk>;
68 clocks = <&soc_refclk60mhz>;
Dmorello.dtsi61 clocks = <&soc_refclk50mhz>;
109 clocks = <&soc_uartclk>, <&soc_refclk50mhz>;
Darm_fpga.dts85 clocks = <&uartclk>, <&bus_refclk>;
Dfvp-ve-Cortex-A5x1.dts55 clocks = <&oscclk3>;
Dn1sdp.dtsi205 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
/trusted-firmware-a-latest/plat/xilinx/zynqmp/pm_service/
Dpm_api_clock.c827 static struct pm_clock clocks[] = { variable
2464 memcpy(name, clocks[clock_id].name, CLK_NAME_LEN); in pm_api_clock_get_name()
2503 clock_nodes = *clocks[clock_id].nodes; in pm_api_clock_get_topology()
2504 num_nodes = clocks[clock_id].num_nodes; in pm_api_clock_get_topology()
2558 clock_nodes = *clocks[clock_id].nodes; in pm_api_clock_get_fixedfactor_params()
2559 num_nodes = clocks[clock_id].num_nodes; in pm_api_clock_get_fixedfactor_params()
2611 clk_parents = *clocks[clock_id].parents; in pm_api_clock_get_parents()
2684 nodes = *clocks[clock_id].nodes; in pm_api_clock_get_max_divisor()
2685 for (i = 0; i < clocks[clock_id].num_nodes; i++) { in pm_api_clock_get_max_divisor()
3061 nodes = *clocks[clock_id].nodes; in pm_clock_has_div()
[all …]
/trusted-firmware-a-latest/docs/plat/
Dqti-msm8916.rst103 the normal world and the necessary clocks remain enabled.
/trusted-firmware-a-latest/docs/plat/marvell/armada/
Dbuild.rst284 clocks according to DDR_TOPOLOGY and CLOCKSPRESET options.
/trusted-firmware-a-latest/docs/
Dchange-log.md3681 …- assign clocks to the correct BL ([7418cf3](https://review.trustedfirmware.org/plugins/gitiles/TF…
3683 …- define secure and non-secure gate clocks ([aaa09b7](https://review.trustedfirmware.org/plugins/g…
3684 …- do not refcount on non-secure clocks in bl32 ([3d69149](https://review.trustedfirmware.org/plugi…
5149 …- set other clocks as always on ([bf39318](https://review.trustedfirmware.org/plugins/gitiles/TF-A…
5863 - Added support for using additional clocks as parents
6012 - Enabled several additional system clocks during initialization
6097 - Non-secure access to clocks and reset domains now depends on their state
6468 fdts DDR memory and XIP rootfs, and set UART clocks to 32MHz
6598 GEM-related clocks