| /trusted-firmware-a-latest/lib/zlib/ |
| D | inffast.c | 65 unsigned bits; /* local strm->bits */ in inflate_fast() local
92 bits = state->bits; in inflate_fast()
101 if (bits < 15) { in inflate_fast()
102 hold += (unsigned long)(*in++) << bits; in inflate_fast()
103 bits += 8; in inflate_fast()
104 hold += (unsigned long)(*in++) << bits; in inflate_fast()
105 bits += 8; in inflate_fast()
109 op = (unsigned)(here->bits); in inflate_fast()
111 bits -= op; in inflate_fast()
123 if (bits < op) { in inflate_fast()
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| D | inflate.c | 122 state->bits = 0; in inflateResetKeep()
223 int ZEXPORT inflatePrime(z_streamp strm, int bits, int value) { in inflatePrime() argument
227 if (bits == 0) in inflatePrime()
230 if (bits < 0) { in inflatePrime()
232 state->bits = 0; in inflatePrime()
235 if (bits > 16 || state->bits + (uInt)bits > 32) return Z_STREAM_ERROR; in inflatePrime()
236 value &= (1L << bits) - 1; in inflatePrime()
237 state->hold += (unsigned)value << state->bits; in inflatePrime()
238 state->bits += (uInt)bits; in inflatePrime()
260 unsigned sym, bits; in fixedtables() local
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| D | inftrees.c | 34 unsigned FAR *bits, unsigned short FAR *work) { in inflate_table() argument
108 root = *bits; in inflate_table()
114 here.bits = (unsigned char)1; in inflate_table()
118 *bits = 1; in inflate_table()
211 here.bits = (unsigned char)(len - drop); in inflate_table()
280 (*table)[low].bits = (unsigned char)root; in inflate_table()
290 here.bits = (unsigned char)(len - drop); in inflate_table()
297 *bits = root; in inflate_table()
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| D | inftrees.h | 26 unsigned char bits; /* bits in this part of the code */ member
62 unsigned FAR *bits, unsigned short FAR *work);
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| D | inflate.h | 103 unsigned bits; /* number of bits in "in" */ member
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| D | zlib.h | 778 int *bits);
792 int bits,
987 int bits,
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| /trusted-firmware-a-latest/plat/nvidia/tegra/soc/t194/drivers/include/ |
| D | t194_nvg.h | 156 } bits; member
165 } bits; member
176 } bits; member
185 } bits; member
196 } bits; member
206 } bits; member
214 } bits; member
245 } bits; member
253 } bits; member
263 } bits; member
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| /trusted-firmware-a-latest/include/drivers/brcm/ |
| D | chimp.h | 48 void bcm_chimp_clrbits(uintptr_t addr, uint32_t bits);
49 void bcm_chimp_setbits(uintptr_t addr, uint32_t bits);
68 static inline void bcm_chimp_clrbits(uintptr_t addr, uint32_t bits) in bcm_chimp_clrbits() argument
71 static inline void bcm_chimp_setbits(uintptr_t addr, uint32_t bits) in bcm_chimp_setbits() argument
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| /trusted-firmware-a-latest/plat/rockchip/rk3288/drivers/soc/ |
| D | soc.h | 89 #define REG_SET_BITS(bits, bits_shift, msk) \ argument
90 (((bits) & (msk)) << (bits_shift))
91 #define REG_WMSK_BITS(bits, bits_shift, msk) \ argument
93 REG_SET_BITS(bits, bits_shift, msk))
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| /trusted-firmware-a-latest/plat/rockchip/common/include/ |
| D | plat_private.h | 52 #define BITS_SHIFT(bits, shift) (bits << (shift)) argument
56 #define BITS_WITH_WMASK(bits, msk, shift)\ argument
57 (BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT)))
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| /trusted-firmware-a-latest/plat/rockchip/rk3368/drivers/soc/ |
| D | soc.h | 125 #define REG_SET_BITS(bits, bits_shift, msk) \ argument
126 (((bits) & (msk)) << (bits_shift))
127 #define REG_WMSK_BITS(bits, bits_shift, msk) \ argument
129 REG_SET_BITS(bits, bits_shift, msk))
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| /trusted-firmware-a-latest/include/bl31/ |
| D | ehf.h | 34 #define EHF_REGISTER_PRIORITIES(priorities, num, bits) \ argument
38 .pri_bits = (bits), \
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| /trusted-firmware-a-latest/docs/security_advisories/ |
| D | security-advisory-tfv-2.rst | 41 A similar issue applies to the ``MDCR_EL3.SPD32`` bits, which control AArch32
42 secure self-hosted invasive debug enablement. TF assigns these bits to ``00``
49 ``MDCR_EL3.SPD32`` bits should be assigned to ``10`` to disable debug exceptions
54 macro. Here the affected bits are ``SDCR.SPD``, which should also be assigned to
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| D | security-advisory-tfv-3.rst | 56 The vulnerability is due to incorrect handling of the execute-never bits in the
59 handles 2 Virtual Address (VA) ranges and so uses 2 bits, ``UXN`` and ``PXN``.
68 of the ``XN``, ``UXN`` or ``PXN`` bits in the translation tables. See the
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| /trusted-firmware-a-latest/drivers/brcm/ |
| D | chimp.c | 49 void bcm_chimp_clrbits(uintptr_t addr, uint32_t bits) in bcm_chimp_clrbits() argument
52 mmio_clrbits_32(CHIMP_INDIRECT_TGT_ADDR(addr), bits); in bcm_chimp_clrbits()
55 void bcm_chimp_setbits(uintptr_t addr, uint32_t bits) in bcm_chimp_setbits() argument
58 mmio_setbits_32(CHIMP_INDIRECT_TGT_ADDR(addr), bits); in bcm_chimp_setbits()
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| /trusted-firmware-a-latest/plat/rockchip/px30/ |
| D | px30_def.h | 16 #define WITH_16BITS_WMSK(bits) (0xffff0000 | (bits)) argument
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| /trusted-firmware-a-latest/docs/components/ |
| D | ffa-manifest-binding.rst | 22 - Must be two 16 bits values (X, Y), concatenated as 31:16 -> X,
292 - A list of (id, mpdir upper bits, mpidr lower bits) tuples describing which
297 - mpidr upper bits: The <u32> describing the upper bits of the 64 bits
299 - mpidr lower bits: The <u32> describing the lower bits of the 64 bits
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| D | exception-handling.rst | 23 Through various control bits in the ``SCR_EL3`` register, the Arm architecture
26 interrupt routing model, TF-A appropriately sets the ``FIQ`` and ``IRQ`` bits of
183 - Of the 8 bits of priority that Arm GIC architecture permits, bit 7 must be 0
187 to use the top *n* of the 7 remaining bits to identify and assign interrupts
188 to individual dispatchers. Choosing *n* bits supports up to 2\ :sup:`n`
189 distinct dispatchers. For example, by choosing 2 additional bits (i.e., bits
197 upper bits of the 8 bits are writeable. In the scheme described above, when
198 choosing *n* bits for priority range assignment, the platform must ensure
199 that at least ``n+1`` top bits of GIC priority are writeable.
302 * This platform uses 2 bits for interrupt association. In total, 3 upper
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| D | arm-sip-service.rst | 423 uint32_t w1: On success, debugfs interface version, 32 bits
424 value with major version number in upper 16 bits and
425 minor version in lower 16 bits.
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| /trusted-firmware-a-latest/drivers/nxp/ddr/fsl-mmdc/ |
| D | fsl_mmdc.c | 24 unsigned int bits) in set_wait_for_bits_clear() argument
30 while ((ddr_in32(ptr) & bits) != 0) { in set_wait_for_bits_clear()
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| /trusted-firmware-a-latest/fdts/ |
| D | stm32mp15-ddr3-1x4Gb-1066-binG.dtsi | 9 * DDR width: 16bits
18 #define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz"
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| D | stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 9 * DDR width: 32bits
18 #define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000kHz"
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| D | stm32mp15-ddr3-1x2Gb-1066-binG.dtsi | 9 * DDR width: 16bits
18 #define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz"
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| /trusted-firmware-a-latest/plat/allwinner/common/ |
| D | arisc_off.S | 20 # r3, so to be patched in the lower 16 bits of the first instruction,
92 l.srli r6, r3, 16 # move mask to lower 16 bits(ds)
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| /trusted-firmware-a-latest/plat/nvidia/tegra/soc/t194/drivers/mce/ |
| D | nvg.c | 259 nvg_hsm_error_ctrl_channel_t status = { .bits = { .corr = 1U, }, }; in nvg_clear_hsm_corr_status()
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