| /trusted-firmware-a-latest/plat/mediatek/drivers/gpio/ |
| D | mtgpio_common.c | 31 uint32_t pos, bit; in mt_set_gpio_dir_chip() local
37 bit = pin % MAX_GPIO_REG_BITS; in mt_set_gpio_dir_chip()
40 mmio_write_32(DIR_BASE + 0x10U * pos + CLR, 1U << bit); in mt_set_gpio_dir_chip()
42 mmio_write_32(DIR_BASE + 0x10U * pos + SET, 1U << bit); in mt_set_gpio_dir_chip()
48 uint32_t pos, bit; in mt_get_gpio_dir_chip() local
54 bit = pin % MAX_GPIO_REG_BITS; in mt_get_gpio_dir_chip()
57 return (((reg & (1U << bit)) != 0U) ? MT_GPIO_DIR_OUT : MT_GPIO_DIR_IN); in mt_get_gpio_dir_chip()
62 uint32_t pos, bit; in mt_set_gpio_out_chip() local
68 bit = pin % MAX_GPIO_REG_BITS; in mt_set_gpio_out_chip()
71 mmio_write_32(DOUT_BASE + 0x10U * pos + CLR, 1U << bit); in mt_set_gpio_out_chip()
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| D | mtgpio_common.h | 94 .bit = _bit, \
102 uint8_t bit; member
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| /trusted-firmware-a-latest/plat/mediatek/mt8183/drivers/gpio/ |
| D | mtgpio.c | 36 uint32_t pos, bit; in mt_set_gpio_dir_chip() local
42 bit = pin % MAX_GPIO_REG_BITS; in mt_set_gpio_dir_chip()
45 mmio_write_32(DIR_BASE + 0x10 * pos + CLR, 1U << bit); in mt_set_gpio_dir_chip()
47 mmio_write_32(DIR_BASE + 0x10 * pos + SET, 1U << bit); in mt_set_gpio_dir_chip()
52 uint32_t pos, bit; in mt_get_gpio_dir_chip() local
58 bit = pin % MAX_GPIO_REG_BITS; in mt_get_gpio_dir_chip()
61 return (((reg & (1U << bit)) != 0) ? GPIO_DIR_OUT : GPIO_DIR_IN); in mt_get_gpio_dir_chip()
66 uint32_t pos, bit; in mt_set_gpio_out_chip() local
72 bit = pin % MAX_GPIO_REG_BITS; in mt_set_gpio_out_chip()
75 mmio_write_32(DOUT_BASE + 0x10 * pos + CLR, 1U << bit); in mt_set_gpio_out_chip()
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| /trusted-firmware-a-latest/plat/mediatek/drivers/iommu/ |
| D | mtk_iommu_priv.h | 22 #define IFR_MST_CFG_ENTRY(idx, bit) \ argument
23 { .cfg_addr_idx = (idx), .r_mmu_en_bit = (bit), }
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| /trusted-firmware-a-latest/docs/perf/ |
| D | performance-monitoring-unit.rst | 48 an identical function and bit field layout as ``PMEVTYPER<n>``. In addition,
84 - If equal to the ``P`` bit it enables the associated ``PMEVCNTR<n>`` at
97 - If different to the ``NSH`` bit it enables the associated ``PMEVCNTR<n>``
104 - If equal to the ``P`` bit it enables the associated ``PMEVCNTR<n>`` at
119 - Setting bit ``P[n]`` to ``1`` enables counter ``PMEVCNTR<n>``.
137 - If set to ``0``, ``PMCCNTR`` will not be affected by this bit and
146 In other words, if this bit is ``0`` then no counters will increment
147 regardless of how the other PMU system registers or bit fields are
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| /trusted-firmware-a-latest/docs/security_advisories/ |
| D | security-advisory-tfv-2.rst | 25 The ``MDCR_EL3.SDD`` bit controls AArch64 secure self-hosted invasive debug
27 Trusted Firmware (TF) unconditionally assign this bit to ``0`` in the early
34 The ``MDCR_EL3.SDD`` bit should be assigned to ``1`` to disable debug exceptions
37 Earlier versions of TF (prior to `commit 495f3d3`_) did not assign this bit.
38 Since the bit has an architecturally ``UNKNOWN`` reset value, earlier versions
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| D | security-advisory-tfv-3.rst | 57 translation tables. The EL3 translation regime uses a single ``XN`` bit to
60 The ``xlat_tables`` library only handles the ``XN`` bit, which maps to ``UXN``
67 non-executable by setting the ``SCTLR_ELx.WXN`` bit. This overrides any value
76 - AArch32 configurations are unaffected. Here the ``XN`` bit controls execution
82 bit. See the ``el3_arch_init_common`` macro in ``el3_common_macros.S``.
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| D | security-advisory-tfv-7.rst | 41 control bit to prevent the re-ordering of stores and loads.
63 - Cortex-A57 and Cortex-A72, by setting bit 55 (Disable load pass store) of
66 - Cortex-A73, by setting bit 3 of ``S3_0_C15_C0_0`` (not documented in the
69 - Cortex-A75, by setting bit 35 (reserved in TRM) of ``CPUACTLR_EL1``
98 - Cortex-A76, by setting and clearing bit 16 (reserved in TRM) of
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| /trusted-firmware-a-latest/plat/rockchip/px30/drivers/soc/ |
| D | soc.h | 75 #define GATE_ID(reg, bit) ((reg) * 16 + (bit)) argument
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| /trusted-firmware-a-latest/plat/xilinx/common/pm_service/ |
| D | pm_ipi.c | 330 uint32_t i, j, c, bit, datain, crcmask, crchighbit; in calculate_crc() local
341 bit = crc & crchighbit; in calculate_crc()
344 bit ^= crchighbit; in calculate_crc()
345 if (bit != 0U) in calculate_crc()
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| /trusted-firmware-a-latest/plat/rockchip/rk3328/drivers/soc/ |
| D | soc.h | 63 #define GATE_ID(reg, bit) ((reg * 16) + bit) argument
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| /trusted-firmware-a-latest/plat/mediatek/drivers/cirq/ |
| D | mt_cirq.c | 240 uint32_t bit = 1U << (cirq_num % 32U); in mt_cirq_set_pol() local
254 mmio_write_32(base, bit); in mt_cirq_set_pol()
268 uint32_t bit = 1U << (cirq_num % 32U); in mt_cirq_mask() local
274 mmio_write_32((cirq_num / 32U) * 4U + CIRQ_MASK_SET_BASE, bit); in mt_cirq_mask()
288 uint32_t bit = 1U << (cirq_num % 32U); in mt_cirq_unmask() local
294 mmio_write_32((cirq_num / 32U) * 4U + CIRQ_MASK_CLR_BASE, bit); in mt_cirq_unmask()
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| /trusted-firmware-a-latest/plat/rockchip/rk3288/drivers/soc/ |
| D | soc.h | 54 #define GATE_ID(reg, bit) (((reg) * 16) + (bit)) argument
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| /trusted-firmware-a-latest/docs/plat/ |
| D | ast2700.rst | 4 Aspeed AST2700 is a 64-bit ARM SoC with 4-cores Cortex-A35 integrated.
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| D | nvidia-tegra.rst | 9 executing both 64-bit AArch64 code, and 32-bit AArch32 code. The Carmel
24 support ARMv8, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code
32 Denver is NVIDIA's own custom-designed, 64-bit, dual-core CPU which is
62 support Armv8-A, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code
147 Protection bit, for Arm Cortex-A57 CPUs, during CPU boot. This flag will
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| D | mt8183.rst | 4 MediaTek 8183 (MT8183) is a 64-bit ARM SoC introduced by MediaTek in early 2018.
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| D | mt8186.rst | 4 MediaTek 8186 (MT8186) is a 64-bit ARM SoC introduced by MediaTek in 2021.
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| D | mt8192.rst | 4 MediaTek 8192 (MT8192) is a 64-bit ARM SoC introduced by MediaTek in 2020.
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| D | mt8195.rst | 4 MediaTek 8195 (MT8195) is a 64-bit ARM SoC introduced by MediaTek in 2021.
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| /trusted-firmware-a-latest/drivers/nxp/auth/csf_hdr_parser/ |
| D | input_bl2_ch3 | 16 # Address can be 64 bit
33 # Address can be 64 bit
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| D | input_bl2_ch3_2 | 16 # Address can be 64 bit
33 # Address can be 64 bit
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| /trusted-firmware-a-latest/plat/rockchip/rk3368/drivers/soc/ |
| D | soc.h | 92 #define GATE_ID(reg, bit) ((reg * 16) + bit) argument
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| /trusted-firmware-a-latest/plat/allwinner/common/ |
| D | arisc_off.S | 27 # respective core bit in CPUX_PWROFF_GATING_REG (0x1f01500).
58 l.bf 1f # don't touch the bit for core 0
61 l.or r5, r5, r6 # set bit to ...
66 l.and r5, r5, r6 # clear bit to ...
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| /trusted-firmware-a-latest/plat/marvell/armada/a8k/common/ |
| D | plat_ble_setup.c | 431 uint8_t parity, bit; in ble_plat_svc_config() local
434 for (bit = 1, parity = (svc[i] & 1); bit < avs_data_bits; bit++) in ble_plat_svc_config()
435 parity ^= (svc[i] >> bit) & 1; in ble_plat_svc_config()
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| /trusted-firmware-a-latest/fdts/ |
| D | corstone700_fvp.dts | 15 * Intel StrataFlash J3 NOR flash: 2 x 16-bit interleaved components
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