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/trusted-firmware-a-latest/plat/rockchip/rk3399/drivers/pmu/
Dpmu.h72 #define SAVE_QOS(array, NAME) \ argument
73 RK3399_CPU_AXI_SAVE_QOS(array, CPU_AXI_##NAME##_QOS_BASE)
74 #define RESTORE_QOS(array, NAME) \ argument
75 RK3399_CPU_AXI_RESTORE_QOS(array, CPU_AXI_##NAME##_QOS_BASE)
77 #define RK3399_CPU_AXI_SAVE_QOS(array, base) do { \ argument
78 array[0] = mmio_read_32(base + CPU_AXI_QOS_ID_COREID); \
79 array[1] = mmio_read_32(base + CPU_AXI_QOS_REVISIONID); \
80 array[2] = mmio_read_32(base + CPU_AXI_QOS_PRIORITY); \
81 array[3] = mmio_read_32(base + CPU_AXI_QOS_MODE); \
82 array[4] = mmio_read_32(base + CPU_AXI_QOS_BANDWIDTH); \
[all …]
/trusted-firmware-a-latest/plat/rockchip/px30/drivers/pmu/
Dpmu.h306 #define PX30_CPU_AXI_SAVE_QOS(array, base) do { \ argument
307 array[0] = mmio_read_32(base + CPU_AXI_QOS_ID_COREID); \
308 array[1] = mmio_read_32(base + CPU_AXI_QOS_REVISIONID); \
309 array[2] = mmio_read_32(base + CPU_AXI_QOS_PRIORITY); \
310 array[3] = mmio_read_32(base + CPU_AXI_QOS_MODE); \
311 array[4] = mmio_read_32(base + CPU_AXI_QOS_BANDWIDTH); \
312 array[5] = mmio_read_32(base + CPU_AXI_QOS_SATURATION); \
313 array[6] = mmio_read_32(base + CPU_AXI_QOS_EXTCONTROL); \
316 #define PX30_CPU_AXI_RESTORE_QOS(array, base) do { \ argument
317 mmio_write_32(base + CPU_AXI_QOS_ID_COREID, array[0]); \
[all …]
/trusted-firmware-a-latest/tools/marvell/doimage/secure/
Dsec_img_7K.cfg5 # CSK keys array - 16 entries total.
14 # index of CSK key in the array. Valid range is 0 to 15
26 # SecureBootControl and EfuseBurnControl registers array
Dsec_img_8K.cfg5 # CSK keys array - 16 entries total.
14 # index of CSK key in the array. Valid range is 0 to 15
26 # SecureBootControl and EfuseBurnControl registers array
/trusted-firmware-a-latest/include/drivers/st/
Dstm32mp_clkfunc.h23 uint32_t *array);
/trusted-firmware-a-latest/lib/psa/
Dmeasured_boot.c17 static void print_byte_array(const uint8_t *array __unused, size_t len __unused) in print_byte_array()
22 if (array == NULL || len == 0U) { in print_byte_array()
26 (void)printf(" %02x", array[i]); in print_byte_array()
/trusted-firmware-a-latest/docs/design/
Dpsci-pd-tree.rst55 removed. A platform must define an array of unsigned chars such that:
57 #. The first entry in the array specifies the number of power domains at the
65 #. The size of the array minus the first entry will be equal to the number of
68 #. The value in each entry in the array is used to find the number of entries
70 all the entries at a level specifies the number of entries in the array for
110 This tree is defined by the platform as the array described above as follows:
143 relationship allows the core nodes to be allocated in a separate array
145 core in the array is the same as the return value from these APIs.
275 The ``psci_non_cpu_pd_nodes`` array will be populated as follows. The value in
296 Each core can find its node in the ``psci_cpu_pd_nodes`` array using the
Dauth-framework.rst645 A CoT is defined as an array of pointers to ``auth_image_desc_t`` structures
663 This CoT consists of an array of pointers to image descriptors and it is
665 ``cot_desc`` must be the name of the array (passing a pointer or any other
690 CoT array, so the descriptors location in the array must match the identifiers.
711 - ``img_auth_methods``: this points to an array which defines the
739 - ``authenticated_data``: this array pointer indicates what authentication
911 is created in the ``authenticated_data`` array for that purpose. In that entry,
Dfirmware-design.rst881 single array and defines symbols that allow the framework to locate and traverse
882 the array, and determine its size.
904 service handler, the framework uses an array of 128 indices that map every
906 indicate the service is not handled. This ``rt_svc_descs_indices[]`` array is
913 ``rt_svc_descs[]`` array.
930 Function ID are combined to index into the ``rt_svc_descs_indices[]`` array. The
933 used as a further index into the ``rt_svc_descs[]`` array to locate the required
1333 Secure interrupt configuration are specified in an array of secure interrupt
1335 ``interrupt_props`` member points to an array of interrupt properties. Each
1336 element of the array specifies the interrupt number and its attributes
[all …]
/trusted-firmware-a-latest/common/
Dfdt_wrappers.c79 uint32_t array[2] = {0, 0}; in fdt_read_uint64() local
82 ret = fdt_read_uint32_array(dtb, node, prop_name, 2, array); in fdt_read_uint64()
87 *value = ((uint64_t)array[0] << 32) | array[1]; in fdt_read_uint64()
/trusted-firmware-a-latest/drivers/st/clk/
Dstm32mp_clkfunc.c177 uint32_t *array) in fdt_rcc_read_uint32_array() argument
191 return fdt_read_uint32_array(fdt, node, prop_name, count, array); in fdt_rcc_read_uint32_array()
/trusted-firmware-a-latest/plat/st/stm32mp1/
Dstm32mp1_scmi.c263 unsigned long *array, size_t *nb_elts, in plat_scmi_clock_rates_array() argument
280 if (array == NULL) { in plat_scmi_clock_rates_array()
283 *array = clk_get_rate(clock->clock_id); in plat_scmi_clock_rates_array()
/trusted-firmware-a-latest/docs/components/fconf/
Damu-bindings.rst44 | | | | the ``reg`` property array of |
62 | ``reg`` | R | array | Represents the counter register |
Dindex.rst84 anything appropriate: structure, array, function, etc..
/trusted-firmware-a-latest/docs/components/
Dffa-manifest-binding.rst31 - value type: <prop-encoded-array>
32 - An array consisting of 4 <u32> values, identifying the UUID of the service
161 - value type: <prop-encoded-array>
253 - value type: <prop-encoded-array>
259 - value type: <prop-encoded-array>
291 - value type: <prop-encoded-array>
Dras.rst225 The platform is expected populate an array using the macros above, and register
227 passing it the name of the array describing the records. Note that the macro
228 must be used in the same file where the array is defined.
267 The platform is expected to define an array of ``struct ras_interrupt``, and
269 ``REGISTER_RAS_INTERRUPTS()``, passing it the name of the array. Note that the
270 macro must be used in the same file where the array is defined.
272 The array of ``struct ras_interrupt`` must be sorted in the increasing order of
318 sorted array of interrupts to look up the error record information associated
Dexception-handling.rst210 The platform expresses the chosen priority levels by declaring an array of
211 priority level descriptors. Each entry in the array is of type
217 The macro ``EHF_PRI_DESC()`` installs the descriptors in the array at a
218 computed index, and not necessarily where the macro is placed in the array.
219 The size of the array might therefore be larger than what it appears to be.
221 array.
223 Finally, this array of descriptors is exposed to |EHF| via the
606 priority scheme, the size of descriptor array exposed with
Dsdei.rst97 - There must be exactly one descriptor in the private array, and none in the
98 shared array.
104 - Explicit events should only be used in the private array.
Dgranule-protection-tables-design.rst102 The programmer should provide the API with an array containing ``pas_region_t``
151 #. Firmware must call ``gpt_init_pas_l1_tables`` with a pointer to an array of
Drmm-el3-comms-spec.rst567 | banks | 8 | ns_dram_bank * | Pointer to 'ns_dram_bank'[] array |
573 and DRAM banks data array pointed by it.
/trusted-firmware-a-latest/docs/resources/diagrams/plantuml/
Dfconf_bl1_load_config.puml28 in global dtb_infos array.
/trusted-firmware-a-latest/plat/allwinner/common/
Darisc_off.S12 # The encoded instructions go into an array defined in
/trusted-firmware-a-latest/docs/process/
Dcoding-guidelines.rst197 of the size of an array is the same.
218 my_struct.h:10:1: error: size of array ‘assert_my_struct_size_mismatch’ is negative
392 to a general, memory-mapped address, an array of pointers or another
/trusted-firmware-a-latest/docs/
Dporting-guide.rst193 the array used for PSCI_STAT_COUNT/RESIDENCY accounting.
954 This function returns an array of SMMU addresses and the actual number of SMMUs
1357 error is usually an indication of an incorrect array size
2518 array of local power states where each index corresponds to a power domain
2538 index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2540 residency statistics. For higher levels (array indices > 0), the residency
2556 index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2558 residency statistics. For higher levels (array indices > 0), the residency
2592 a pointer to an array of platform specific local power state ``states`` (second
2595 is expected to traverse this array of upto ``ncpus`` (third argument) and return
[all …]
/trusted-firmware-a-latest/docs/getting_started/
Dpsci-lib-integration-guide.rst368 For example, SP-MIN stores the pointers in the array ``sp_min_cpu_ctx_ptr``

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