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Searched refs:ap_index (Results 1 – 19 of 19) sorted by relevance

/trusted-firmware-a-latest/drivers/marvell/
Dcache_llc.c21 #define CCU_HTC_CR(ap_index) (MVEBU_CCU_BASE(ap_index) + 0x200) argument
26 void llc_cache_sync(int ap_index) in llc_cache_sync() argument
28 mmio_write_32(LLC_SYNC(ap_index), 0); in llc_cache_sync()
32 void llc_flush_all(int ap_index) in llc_flush_all() argument
34 mmio_write_32(LLC_CLEAN_INV_WAY(ap_index), LLC_ALL_WAYS_MASK); in llc_flush_all()
35 llc_cache_sync(ap_index); in llc_flush_all()
38 void llc_clean_all(int ap_index) in llc_clean_all() argument
40 mmio_write_32(LLC_CLEAN_WAY(ap_index), LLC_ALL_WAYS_MASK); in llc_clean_all()
41 llc_cache_sync(ap_index); in llc_clean_all()
44 void llc_inv_all(int ap_index) in llc_inv_all() argument
[all …]
Dccu.c70 static void dump_ccu(int ap_index) in dump_ccu() argument
80 win_cr = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); in dump_ccu()
84 alr = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index, in dump_ccu()
86 ahr = mmio_read_32(CCU_WIN_AHR_OFFSET(ap_index, in dump_ccu()
94 win_cr = mmio_read_32(CCU_WIN_GCR_OFFSET(ap_index)); in dump_ccu()
117 int ccu_is_win_enabled(int ap_index, uint32_t win_id) in ccu_is_win_enabled() argument
119 return mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)) & in ccu_is_win_enabled()
123 void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id) in ccu_enable_win() argument
138 mmio_write_32(CCU_WIN_ALR_OFFSET(ap_index, win_id), alr); in ccu_enable_win()
139 mmio_write_32(CCU_WIN_AHR_OFFSET(ap_index, win_id), ahr); in ccu_enable_win()
[all …]
Dgwin.c67 static void gwin_enable_window(int ap_index, struct addr_map_win *win, in gwin_enable_window() argument
85 mmio_write_32(GWIN_ALR_OFFSET(ap_index, win_num), alr); in gwin_enable_window()
86 mmio_write_32(GWIN_AHR_OFFSET(ap_index, win_num), ahr); in gwin_enable_window()
89 mmio_write_32(GWIN_CR_OFFSET(ap_index, win_num), in gwin_enable_window()
93 static void gwin_disable_window(int ap_index, uint32_t win_num) in gwin_disable_window() argument
97 win_reg = mmio_read_32(GWIN_CR_OFFSET(ap_index, win_num)); in gwin_disable_window()
99 mmio_write_32(GWIN_CR_OFFSET(ap_index, win_num), win_reg); in gwin_disable_window()
110 void gwin_temp_win_insert(int ap_index, struct addr_map_win *win, int size) in gwin_temp_win_insert() argument
117 gwin_enable_window(ap_index, win, win_id); in gwin_temp_win_insert()
126 void gwin_temp_win_remove(int ap_index, struct addr_map_win *win, int size) in gwin_temp_win_remove() argument
[all …]
Dio_win.c62 static void io_win_enable_window(int ap_index, struct addr_map_win *win, in io_win_enable_window() argument
86 mmio_write_32(IO_WIN_ALR_OFFSET(ap_index, win_num), alr); in io_win_enable_window()
87 mmio_write_32(IO_WIN_AHR_OFFSET(ap_index, win_num), ahr); in io_win_enable_window()
90 mmio_write_32(IO_WIN_CR_OFFSET(ap_index, win_num), win->target_id); in io_win_enable_window()
93 static void io_win_disable_window(int ap_index, uint32_t win_num) in io_win_disable_window() argument
102 win_reg = mmio_read_32(IO_WIN_ALR_OFFSET(ap_index, win_num)); in io_win_disable_window()
104 mmio_write_32(IO_WIN_ALR_OFFSET(ap_index, win_num), win_reg); in io_win_disable_window()
115 void iow_temp_win_insert(int ap_index, struct addr_map_win *win, int size) in iow_temp_win_insert() argument
122 io_win_enable_window(ap_index, win, win_id); in iow_temp_win_insert()
131 void iow_temp_win_remove(int ap_index, struct addr_map_win *win, int size) in iow_temp_win_remove() argument
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/trusted-firmware-a-latest/include/drivers/marvell/
Dcache_llc.h47 void llc_cache_sync(int ap_index);
48 void llc_flush_all(int ap_index);
49 void llc_clean_all(int ap_index);
50 void llc_inv_all(int ap_index);
51 void llc_disable(int ap_index);
52 void llc_enable(int ap_index, int excl_mode);
53 int llc_is_exclusive(int ap_index);
54 void llc_runtime_enable(int ap_index);
56 int llc_sram_enable(int ap_index, int size);
57 void llc_sram_disable(int ap_index);
[all …]
Dccu.h42 void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id);
43 void ccu_temp_win_insert(int ap_index, struct addr_map_win *win, int size);
44 void ccu_temp_win_remove(int ap_index, struct addr_map_win *win, int size);
45 void ccu_dram_win_config(int ap_index, struct addr_map_win *win);
46 void ccu_dram_target_set(int ap_index, uint32_t target);
49 int ccu_is_win_enabled(int ap_index, uint32_t win_id);
Dgwin.h15 int init_gwin(int ap_index);
16 void gwin_temp_win_insert(int ap_index, struct addr_map_win *win, int size);
17 void gwin_temp_win_remove(int ap_index, struct addr_map_win *win, int size);
Dio_win.h15 int init_io_win(int ap_index);
16 void iow_temp_win_insert(int ap_index, struct addr_map_win *win, int size);
17 void iow_temp_win_remove(int ap_index, struct addr_map_win *win, int size);
/trusted-firmware-a-latest/drivers/marvell/mc_trustzone/
Dmc_trustzone.c32 void tz_enable_win(int ap_index, const struct addr_map_win *win, int win_id) in tz_enable_win() argument
64 mmio_write_32(MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap_index, win_id), val); in tz_enable_win()
67 MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap_index, win_id), in tz_enable_win()
68 mmio_read_32(MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap_index, win_id))); in tz_enable_win()
70 mmio_write_32(MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap_index, win_id), in tz_enable_win()
74 MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap_index, win_id), in tz_enable_win()
75 mmio_read_32(MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap_index, win_id))); in tz_enable_win()
Dmc_trustzone.h25 void tz_enable_win(int ap_index, const struct addr_map_win *win, int win_id);
/trusted-firmware-a-latest/plat/marvell/armada/a8k/a70x0_mochabin/board/
Dmarvell_plat_config.c54 uint32_t marvell_get_io_win_gcr_target(int ap_index) in marvell_get_io_win_gcr_target() argument
59 int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_io_win_memory_map() argument
124 int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_ccu_memory_map() argument
/trusted-firmware-a-latest/plat/marvell/armada/a8k/a70x0/board/
Dmarvell_plat_config.c52 uint32_t marvell_get_io_win_gcr_target(int ap_index) in marvell_get_io_win_gcr_target() argument
57 int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_io_win_memory_map() argument
122 int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_ccu_memory_map() argument
/trusted-firmware-a-latest/plat/marvell/armada/a8k/a70x0_amc/board/
Dmarvell_plat_config.c49 uint32_t marvell_get_io_win_gcr_target(int ap_index) in marvell_get_io_win_gcr_target() argument
54 int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_io_win_memory_map() argument
113 int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_ccu_memory_map() argument
/trusted-firmware-a-latest/plat/marvell/octeontx/otx2/t91/t9130/board/
Dmarvell_plat_config.c70 uint32_t marvell_get_io_win_gcr_target(int ap_index) in marvell_get_io_win_gcr_target() argument
79 int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_io_win_memory_map() argument
173 int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_ccu_memory_map() argument
/trusted-firmware-a-latest/plat/marvell/armada/a8k/a80x0_mcbin/board/
Dmarvell_plat_config.c90 uint32_t marvell_get_io_win_gcr_target(int ap_index) in marvell_get_io_win_gcr_target() argument
95 int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_io_win_memory_map() argument
181 int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_ccu_memory_map() argument
/trusted-firmware-a-latest/plat/marvell/octeontx/otx2/t91/t9130_cex7_eval/board/
Dmarvell_plat_config.c93 uint32_t marvell_get_io_win_gcr_target(int ap_index) in marvell_get_io_win_gcr_target() argument
102 int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_io_win_memory_map() argument
205 int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_ccu_memory_map() argument
/trusted-firmware-a-latest/plat/marvell/armada/a8k/a80x0_puzzle/board/
Dmarvell_plat_config.c94 uint32_t marvell_get_io_win_gcr_target(int ap_index) in marvell_get_io_win_gcr_target() argument
99 int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_io_win_memory_map() argument
182 int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_ccu_memory_map() argument
/trusted-firmware-a-latest/plat/marvell/armada/a8k/common/include/
Da8k_plat_def.h36 #define MVEBU_IO_WIN_BASE(ap_index) (MVEBU_RFU_BASE) argument
43 #define MVEBU_CCU_BASE(ap_index) (MVEBU_REGS_BASE + 0x4000) argument
46 #define MVEBU_LLC_BASE(ap_index) (MVEBU_REGS_BASE + 0x8000) argument
/trusted-firmware-a-latest/plat/marvell/armada/a8k/a80x0/board/
Dmarvell_plat_config.c60 uint32_t marvell_get_io_win_gcr_target(int ap_index) in marvell_get_io_win_gcr_target() argument
65 int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_io_win_memory_map() argument