Searched refs:TZC_REGION_ACCESS_RDWR (Results 1 – 13 of 13) sorted by relevance
24 (TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) | \25 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_GPU_ID) | \26 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_LCD_ID) | \27 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_MDMA_ID) | \28 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_M4_ID) | \29 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DMA_ID) | \30 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_HOST_ID) | \31 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_OTG_ID) | \32 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID) | \33 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_ETH_ID) | \[all …]
24 (TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) | \25 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_LCD_ID) | \26 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_MDMA_ID) | \27 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DMA_ID) | \28 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_HOST_ID) | \29 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_OTG_ID) | \30 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID) | \31 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_ETH_ID) | \32 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DCMIPP_ID) | \33 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DAP_ID))
58 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \59 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \60 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \61 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DMA)) | \62 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DMA2)) | \63 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \64 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \65 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO))
42 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \43 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \44 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \45 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \46 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \47 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO))
39 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \40 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \41 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \42 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \43 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \44 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO))
222 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \223 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \224 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \225 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \226 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \227 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \228 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \229 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \230 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \231 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT))
54 (TZC_REGION_ACCESS_RDWR(JUNO_TZC400_NSAID_FPGA_MEDIA_SECURE) | \58 (TZC_REGION_ACCESS_RDWR(JUNO_TZC400_NSAID_FPGA_VIDEO_PROTECTED))61 (TZC_REGION_ACCESS_RDWR(JUNO_TZC400_NSAID_FPGA_VIDEO_PRIVATE))
38 (TZC_REGION_ACCESS_RDWR(JUNO_ETHOSN_TZC400_NSAID_FW_PROT))40 (TZC_REGION_ACCESS_RDWR(JUNO_ETHOSN_TZC400_NSAID_DATA_RW_PROT) | \
239 TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_DEFAULT) | \240 TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_PCI) | \241 TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_AP) | \242 TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_VIRTIO) | \243 TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_VIRTIO_OLD))
386 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \387 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \388 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \389 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \390 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD))
81 #define TZC_REGION_ACCESS_RDWR(nsaid) \ macro
75 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID)
294 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT))
