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Searched refs:SYSMGR_ECC_DDR1_MASK (Results 1 – 6 of 6) sorted by relevance

/trusted-firmware-a-latest/plat/intel/soc/common/include/
Dsocfpga_system_manager.h29 #define SYSMGR_ECC_DDR1_MASK BIT(17) macro
Dsocfpga_sip_svc.h154 SYSMGR_ECC_DDR1_MASK)
/trusted-firmware-a-latest/plat/intel/soc/n5x/include/
Dn5x_system_manager.h182 #define SYSMGR_ECC_DDR1_MASK BIT(17) macro
/trusted-firmware-a-latest/plat/intel/soc/stratix10/include/
Ds10_system_manager.h178 #define SYSMGR_ECC_DDR1_MASK BIT(17) macro
/trusted-firmware-a-latest/plat/intel/soc/agilex/include/
Dagilex_system_manager.h179 #define SYSMGR_ECC_DDR1_MASK BIT(17) macro
/trusted-firmware-a-latest/plat/intel/soc/agilex5/include/
Dagilex5_system_manager.h182 #define SYSMGR_ECC_DDR1_MASK BIT(17) macro