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Searched refs:SOCFPGA_SYSMGR_PHY_DQS_TIMING_REG (Results 1 – 4 of 4) sorted by relevance

/trusted-firmware-a-latest/plat/intel/soc/n5x/include/
Dn5x_system_manager.h61 #define SOCFPGA_SYSMGR_PHY_DQS_TIMING_REG 0x110 macro
/trusted-firmware-a-latest/plat/intel/soc/stratix10/include/
Ds10_system_manager.h61 #define SOCFPGA_SYSMGR_PHY_DQS_TIMING_REG 0x110 macro
/trusted-firmware-a-latest/plat/intel/soc/agilex/include/
Dagilex_system_manager.h61 #define SOCFPGA_SYSMGR_PHY_DQS_TIMING_REG 0x110 macro
/trusted-firmware-a-latest/plat/intel/soc/agilex5/include/
Dagilex5_system_manager.h61 #define SOCFPGA_SYSMGR_PHY_DQS_TIMING_REG 0x110 macro