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Searched refs:SOCFPGA_LWSOC2FPGA_SCR_REG_BASE (Results 1 – 5 of 5) sorted by relevance

/trusted-firmware-a-latest/plat/intel/soc/stratix10/include/
Dsocfpga_plat_def.h40 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300 macro
/trusted-firmware-a-latest/plat/intel/soc/agilex/include/
Dsocfpga_plat_def.h41 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300 macro
/trusted-firmware-a-latest/plat/intel/soc/n5x/include/
Dsocfpga_plat_def.h41 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE U(0xffd21300) macro
/trusted-firmware-a-latest/plat/intel/soc/agilex5/include/
Dsocfpga_plat_def.h52 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0x10d21300 macro
/trusted-firmware-a-latest/plat/intel/soc/common/soc/
Dsocfpga_firewall.c129 mmio_write_32(SOCFPGA_LWSOC2FPGA_SCR_REG_BASE, DISABLE_BRIDGE_FIREWALL); in enable_ns_bridge_access()