Home
last modified time | relevance | path

Searched refs:RSTMGR_CPUxRESETBASELOW_CPU3 (Results 1 – 2 of 2) sorted by relevance

/trusted-firmware-a-latest/plat/intel/soc/common/include/
Dsocfpga_reset_manager.h221 #define RSTMGR_CPUxRESETBASELOW_CPU3 0x10D110B0 macro
/trusted-firmware-a-latest/plat/intel/soc/agilex5/
Dbl31_plat_setup.c255 mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU3, (uint64_t) plat_secondary_cpus_bl31_entry >> 2); in bl31_plat_set_secondary_cpu_entrypoint()