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Searched refs:RSTMGR_CPUxRESETBASELOW_CPU1 (Results 1 – 2 of 2) sorted by relevance

/trusted-firmware-a-latest/plat/intel/soc/common/include/
Dsocfpga_reset_manager.h217 #define RSTMGR_CPUxRESETBASELOW_CPU1 0x10D110A0 macro
/trusted-firmware-a-latest/plat/intel/soc/agilex5/
Dbl31_plat_setup.c254 mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU1, (uint64_t) plat_secondary_cpus_bl31_entry >> 2); in bl31_plat_set_secondary_cpu_entrypoint()