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Searched refs:RSTMGR_CPUxRESETBASELOW_CPU0 (Results 1 – 2 of 2) sorted by relevance

/trusted-firmware-a-latest/plat/intel/soc/common/include/
Dsocfpga_reset_manager.h215 #define RSTMGR_CPUxRESETBASELOW_CPU0 0x10D11098 macro
/trusted-firmware-a-latest/plat/intel/soc/agilex5/
Dbl31_plat_setup.c249 mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU0, in bl31_plat_set_secondary_cpu_entrypoint()