Searched refs:ROOT_CPUTOP_ADDR (Results 1 – 10 of 10) sorted by relevance
| /trusted-firmware-a-latest/plat/mediatek/mt8183/drivers/spm/ |
| D | spm.c | 99 mmio_write_32(ROOT_CPUTOP_ADDR, 0x10006204); in spm_set_cpu_status()
102 mmio_write_32(ROOT_CPUTOP_ADDR, 0x10006218); in spm_set_cpu_status()
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| D | spm.h | 263 #define ROOT_CPUTOP_ADDR (SPM_BASE + 0x570) macro
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| /trusted-firmware-a-latest/plat/mediatek/drivers/spm/mt8188/ |
| D | mt_spm_internal.c | 86 mmio_write_32(ROOT_CPUTOP_ADDR, BIT(cpu)); in __spm_set_cpu_status()
436 mmio_write_32(EXT_INT_WAKEUP_REQ_CLR, mmio_read_32(ROOT_CPUTOP_ADDR)); in __spm_ext_int_wakeup_req_clr()
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| /trusted-firmware-a-latest/plat/mediatek/mt8195/drivers/spm/ |
| D | mt_spm_internal.c | 135 mmio_write_32(ROOT_CPUTOP_ADDR, (1U << cpu)); in __spm_set_cpu_status()
509 mmio_write_32(EXT_INT_WAKEUP_REQ_CLR, mmio_read_32(ROOT_CPUTOP_ADDR)); in __spm_ext_int_wakeup_req_clr()
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| D | mt_spm_reg.h | 158 #define ROOT_CPUTOP_ADDR (SPM_BASE + 0x2A0) macro
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| /trusted-firmware-a-latest/plat/mediatek/mt8192/drivers/spm/ |
| D | mt_spm_internal.c | 128 mmio_write_32(ROOT_CPUTOP_ADDR, (1U << cpu)); in __spm_set_cpu_status()
547 mmio_write_32(EXT_INT_WAKEUP_REQ_CLR, mmio_read_32(ROOT_CPUTOP_ADDR)); in __spm_ext_int_wakeup_req_clr()
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| D | mt_spm_reg.h | 161 #define ROOT_CPUTOP_ADDR (SPM_BASE + 0x2A0) macro
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| /trusted-firmware-a-latest/plat/mediatek/mt8186/drivers/spm/ |
| D | mt_spm_internal.c | 118 mmio_write_32(ROOT_CPUTOP_ADDR, BIT(cpu)); in __spm_set_cpu_status()
582 mmio_write_32(EXT_INT_WAKEUP_REQ_CLR, mmio_read_32(ROOT_CPUTOP_ADDR)); in __spm_ext_int_wakeup_req_clr()
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| D | mt_spm_reg.h | 142 #define ROOT_CPUTOP_ADDR (SPM_BASE + 0x2A0) macro
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| /trusted-firmware-a-latest/plat/mediatek/mt8188/include/ |
| D | spm_reg.h | 146 #define ROOT_CPUTOP_ADDR (SPM_BASE + 0x2A0) macro
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