Searched refs:ROM (Results 1 – 25 of 47) sorted by relevance
12
| /trusted-firmware-a-latest/bl1/ |
| D | bl1.ld.S | 22 ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE
27 ROM_REGION_START = ORIGIN(ROM);
28 ROM_REGION_LENGTH = LENGTH(ROM);
49 } >ROM
54 } >ROM
58 } >ROM
80 } >ROM
101 } >ROM
113 DATA_SECTION >RAM AT>ROM
|
| /trusted-firmware-a-latest/docs/components/ |
| D | romlib-design.rst | 1 Library at ROM
4 This document provides an overview of the "library at ROM" implementation in
10 The "library at ROM" feature allows platforms to build a library of functions to
11 be placed in ROM. This reduces SRAM usage by utilising the available space in
12 ROM. The "library at ROM" contains a jump table with the list of functions that
13 are placed in ROM. The capabilities of the "library at ROM" are:
17 2. Functions can be patched after they have been programmed into ROM.
19 3. Platform-specific libraries can be placed in ROM.
29 Library at ROM is described by an index file with the list of functions to be
30 placed in ROM. The index file is platform specific and its format is:
[all …]
|
| /trusted-firmware-a-latest/bl2/ |
| D | bl2_el3.ld.S | 16 ROM (rx): ORIGIN = BL2_RO_BASE, LENGTH = BL2_RO_LIMIT - BL2_RO_BASE
30 # define ROM RAM macro
37 ROM_REGION_START = ORIGIN(ROM);
38 ROM_REGION_LENGTH = LENGTH(ROM);
73 } >ROM
86 } >ROM
117 } >ROM
133 DATA_SECTION >RAM AT>ROM
|
| /trusted-firmware-a-latest/lib/romlib/ |
| D | romlib.ld.S | 11 ROM (rx): ORIGIN = ROMLIB_RO_BASE, LENGTH = ROMLIB_RO_LIMIT - ROMLIB_RO_BASE
26 } >ROM
36 } >RAM AT>ROM
|
| /trusted-firmware-a-latest/docs/plat/st/ |
| D | stm32mpus.rst | 11 The STM32 MPU resets in the ROM code of the Cortex-A.
14 The ROM code boot sequence loads the TF-A binary image from boot device
18 for ROM code is able to load this image.
23 Only BL2 (with STM32 header) is loaded by ROM code. The other binaries are
30 ROM code -> BL2 (compiled with RESET_TO_BL2) -> OP-TEE -> BL33 (U-Boot)
|
| /trusted-firmware-a-latest/plat/nxp/soc-ls1046a/ |
| D | soc.def | 43 # Area of OCRAM reserved by ROM code
62 # After BL2 bin, OCRAM is used by ROM Code:
65 # After ROM Code, OCRAM is used by CSF header.
|
| /trusted-firmware-a-latest/plat/nxp/soc-ls1043a/ |
| D | soc.def | 43 # Area of OCRAM reserved by ROM code
62 # After BL2 bin, OCRAM is used by ROM Code:
65 # After ROM Code, OCRAM is used by CSF header.
|
| /trusted-firmware-a-latest/docs/plat/ |
| D | intel-agilex.rst | 6 Upon boot, Boot ROM loads bl2 into OCRAM. Bl2 subsequently initializes
11 Boot ROM --> Trusted Firmware-A --> UEFI
45 BL33=PEI.ROM
|
| D | intel-stratix10.rst | 6 Upon boot, Boot ROM loads bl2 into OCRAM. Bl2 subsequently initializes
11 Boot ROM --> Trusted Firmware-A --> UEFI
45 BL33=PEI.ROM
|
| D | socionext-uniphier.rst | 7 UniPhier SoC family implements its internal boot ROM, which loads 64KB [1]_
10 It is useful for platforms with non-TF-A boot ROM, like UniPhier. Here, a
27 ROM (and verified if the chip fuses are blown).
33 1. The Boot ROM
35 This is hard-wired ROM, so never corrupted. It loads the UniPhier BL (with
|
| D | npcm845x.rst | 9 This SoC includes secured components, i.e., bootblock stored in ROM,
|
| D | brcm-stingray.rst | 10 On Poweron, Boot ROM will load bl2 image and Bl2 will initialize the hardware,
|
| D | qemu.rst | 96 ``fip.bin`` to create a boot ROM that is flashed onto secure FLASH0 with the
129 2. Concatenate ``bl1.bin`` and ``fip.bin`` to create the boot ROM
147 or ROM memory. QEMU loads the binary into the region corresponding to
|
| D | imx8.rst | 54 with certain offset for BOOT ROM. The system controller firmware,
|
| D | imx8m.rst | 47 with certain offset for BOOT ROM. the u-boot and imx-mkimage will be upstreamed
76 Boot (HABv4), which is implemented via ROM Vector Table (RVT) API to
|
| D | imx9.rst | 47 with certain offset for BOOT ROM.
|
| /trusted-firmware-a-latest/plat/nxp/soc-ls1088a/ |
| D | soc.def | 46 # 0x18000000 - 0x18009fff -> Used by ROM code, (TBD - can it be used for xlat tables)
54 # Area of OCRAM reserved by ROM code
|
| /trusted-firmware-a-latest/plat/nxp/soc-ls1028a/ |
| D | soc.def | 47 # 0x18000000 - 0x18009fff -> Used by ROM code
57 # Area of OCRAM reserved by ROM code
|
| /trusted-firmware-a-latest/plat/nxp/soc-lx2160a/ |
| D | soc.def | 38 # Area of OCRAM reserved by ROM code
79 # 0x18000000 - 0x18009fff -> Used by ROM code
|
| /trusted-firmware-a-latest/docs/resources/diagrams/plantuml/ |
| D | tfa_dfd.puml | 51 bl1 [label="Boot ROM\n(BL1)" fillcolor="#ddffb3"];
|
| D | tfa_rss_dfd.puml | 52 bl1 [label="Boot ROM\n(BL1)" fillcolor="#ddffb3"];
|
| D | tfa_arm_cca_dfd.puml | 52 bl1 [label="Boot ROM\n(BL1)" fillcolor="#ddffb3"];
|
| D | rss_measured_boot_flow.puml | 21 Rnote over RSS_BL1_1: ROM code, XIP
|
| /trusted-firmware-a-latest/docs/getting_started/ |
| D | image-terminology.rst | 52 AP Boot ROM: ``AP_BL1``
112 SCP Boot ROM: ``SCP_BL1`` (previously ``BL0``)
144 AP Firmware Update Boot ROM: ``AP_NS_BL1U``
188 MCP Boot ROM: ``MCP_BL1``
|
| /trusted-firmware-a-latest/docs/plat/arm/arm_fpga/ |
| D | index.rst | 58 Defaults to 0x1000, which is normally in the "ROM" space of the typical
84 as some simple ROM trampoline code (required by the Arm FPGA boot flow) and
|
12
