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Searched refs:MVEBU_CPU_1_RESET_REG (Results 1 – 1 of 1) sorted by relevance

/trusted-firmware-a-latest/plat/marvell/armada/a3k/common/
Dplat_pm.c39 #define MVEBU_CPU_1_RESET_REG (MVEBU_REGS_BASE + 0xD00C) macro
270 mmio_clrbits_32(MVEBU_CPU_1_RESET_REG, BIT(MVEBU_CPU_1_RESET_BIT)); in a3700_pwr_domain_on()
271 mmio_setbits_32(MVEBU_CPU_1_RESET_REG, BIT(MVEBU_CPU_1_RESET_BIT)); in a3700_pwr_domain_on()