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Searched refs:MP_CPUSYS_TOP_MP0_DCM_CFG0 (Results 1 – 6 of 6) sorted by relevance

/trusted-firmware-a-latest/plat/mediatek/drivers/dcm/mt8188/
Dmtk_dcm_utils.c90 ret &= dcm_check_state(MP_CPUSYS_TOP_MP0_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm_is_on()
107 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
118 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
349 ret &= dcm_check_state(MP_CPUSYS_TOP_MP0_DCM_CFG0, in dcm_mp_cpusys_top_mp0_qdcm_is_on()
363 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, in dcm_mp_cpusys_top_mp0_qdcm()
371 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, in dcm_mp_cpusys_top_mp0_qdcm()
Dmtk_dcm_utils.h29 #define MP_CPUSYS_TOP_MP0_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x4880) macro
/trusted-firmware-a-latest/plat/mediatek/mt8186/drivers/dcm/
Dmtk_dcm_utils.c88 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG0) & in dcm_mp_cpusys_top_apb_dcm_is_on()
105 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
116 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
439 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG0) & in dcm_mp_cpusys_top_mp0_qdcm_is_on()
450 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, in dcm_mp_cpusys_top_mp0_qdcm()
455 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, in dcm_mp_cpusys_top_mp0_qdcm()
Dmtk_dcm_utils.h27 #define MP_CPUSYS_TOP_MP0_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x4880) macro
/trusted-firmware-a-latest/plat/mediatek/mt8195/drivers/dcm/
Dmtk_dcm_utils.c106 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG0) & in dcm_mp_cpusys_top_apb_dcm_is_on()
123 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
134 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
418 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG0) & in dcm_mp_cpusys_top_mp0_qdcm_is_on()
432 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, in dcm_mp_cpusys_top_mp0_qdcm()
440 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, in dcm_mp_cpusys_top_mp0_qdcm()
Dmtk_dcm_utils.h29 #define MP_CPUSYS_TOP_MP0_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x4880) macro