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Searched refs:MP_CPUSYS_TOP_MCUSYS_DCM_CFG0 (Results 1 – 6 of 6) sorted by relevance

/trusted-firmware-a-latest/plat/mediatek/drivers/dcm/mt8188/
Dmtk_dcm_utils.c36 ret &= dcm_check_state(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm_is_on()
53 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
64 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
87 ret &= dcm_check_state(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm_is_on()
104 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
115 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
Dmtk_dcm_utils.h28 #define MP_CPUSYS_TOP_MCUSYS_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x25c0) macro
/trusted-firmware-a-latest/plat/mediatek/mt8186/drivers/dcm/
Dmtk_dcm_utils.c40 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) & in dcm_mp_cpusys_top_adb_dcm_is_on()
54 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
62 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
85 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) & in dcm_mp_cpusys_top_apb_dcm_is_on()
102 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
113 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
Dmtk_dcm_utils.h26 #define MP_CPUSYS_TOP_MCUSYS_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x25c0) macro
/trusted-firmware-a-latest/plat/mediatek/mt8195/drivers/dcm/
Dmtk_dcm_utils.c52 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) & in dcm_mp_cpusys_top_adb_dcm_is_on()
69 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
80 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
103 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) & in dcm_mp_cpusys_top_apb_dcm_is_on()
120 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
131 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
Dmtk_dcm_utils.h27 #define MP_CPUSYS_TOP_MCUSYS_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x25c0) macro