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Searched refs:MP_CPUSYS_TOP_CPU_PLLDIV_CFG0 (Results 1 – 6 of 6) sorted by relevance

/trusted-firmware-a-latest/plat/mediatek/mt8195/drivers/dcm/
Dmtk_dcm_utils.h20 #define MP_CPUSYS_TOP_CPU_PLLDIV_CFG0 (MP_CPUSYS_TOP_BASE + 0x22a0) macro
Dmtk_dcm_utils.c247 ret &= ((mmio_read_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0) & in dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on()
258 mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0, in dcm_mp_cpusys_top_cpu_pll_div_0_dcm()
263 mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0, in dcm_mp_cpusys_top_cpu_pll_div_0_dcm()
/trusted-firmware-a-latest/plat/mediatek/drivers/dcm/mt8188/
Dmtk_dcm_utils.h21 #define MP_CPUSYS_TOP_CPU_PLLDIV_CFG0 (MP_CPUSYS_TOP_BASE + 0x22a0) macro
Dmtk_dcm_utils.c210 return dcm_check_state(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0, in dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on()
219 mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0, in dcm_mp_cpusys_top_cpu_pll_div_0_dcm()
224 mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0, in dcm_mp_cpusys_top_cpu_pll_div_0_dcm()
/trusted-firmware-a-latest/plat/mediatek/mt8186/drivers/dcm/
Dmtk_dcm_utils.h22 #define MP_CPUSYS_TOP_CPU_PLLDIV_CFG0 (MP_CPUSYS_TOP_BASE + 0x22a0) macro
Dmtk_dcm_utils.c262 ret &= ((mmio_read_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0) & in dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on()
273 mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0, in dcm_mp_cpusys_top_cpu_pll_div_0_dcm()
278 mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0, in dcm_mp_cpusys_top_cpu_pll_div_0_dcm()