Home
last modified time | relevance | path

Searched refs:MP_CPUSYS_TOP_BASE (Results 1 – 4 of 4) sorted by relevance

/trusted-firmware-a-latest/plat/mediatek/mt8192/drivers/dcm/
Dmtk_dcm_utils.h16 #define MP_CPUSYS_TOP_BASE (MCUCFG_BASE + 0x8000) macro
20 #define CPU_PLLDIV_CFG0 (MP_CPUSYS_TOP_BASE + 0x22a0)
21 #define CPU_PLLDIV_CFG1 (MP_CPUSYS_TOP_BASE + 0x22a4)
22 #define CPU_PLLDIV_CFG2 (MP_CPUSYS_TOP_BASE + 0x22a8)
23 #define CPU_PLLDIV_CFG3 (MP_CPUSYS_TOP_BASE + 0x22ac)
24 #define CPU_PLLDIV_CFG4 (MP_CPUSYS_TOP_BASE + 0x22b0)
25 #define BUS_PLLDIV_CFG (MP_CPUSYS_TOP_BASE + 0x22e0)
26 #define MCSI_DCM0 (MP_CPUSYS_TOP_BASE + 0x2440)
27 #define MP_ADB_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2500)
28 #define MP_ADB_DCM_CFG4 (MP_CPUSYS_TOP_BASE + 0x2510)
[all …]
/trusted-firmware-a-latest/plat/mediatek/mt8195/drivers/dcm/
Dmtk_dcm_utils.h16 #define MP_CPUSYS_TOP_BASE (MCUCFG_BASE + 0x8000) macro
20 #define MP_CPUSYS_TOP_CPU_PLLDIV_CFG0 (MP_CPUSYS_TOP_BASE + 0x22a0)
21 #define MP_CPUSYS_TOP_CPU_PLLDIV_CFG1 (MP_CPUSYS_TOP_BASE + 0x22a4)
22 #define MP_CPUSYS_TOP_BUS_PLLDIV_CFG (MP_CPUSYS_TOP_BASE + 0x22e0)
23 #define MP_CPUSYS_TOP_MCSIC_DCM0 (MP_CPUSYS_TOP_BASE + 0x2440)
24 #define MP_CPUSYS_TOP_MP_ADB_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2500)
25 #define MP_CPUSYS_TOP_MP_ADB_DCM_CFG4 (MP_CPUSYS_TOP_BASE + 0x2510)
26 #define MP_CPUSYS_TOP_MP_MISC_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2518)
27 #define MP_CPUSYS_TOP_MCUSYS_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x25c0)
29 #define MP_CPUSYS_TOP_MP0_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x4880)
[all …]
/trusted-firmware-a-latest/plat/mediatek/drivers/dcm/mt8188/
Dmtk_dcm_utils.h16 #define MP_CPUSYS_TOP_BASE (MCUCFG_BASE + 0x8000) macro
21 #define MP_CPUSYS_TOP_CPU_PLLDIV_CFG0 (MP_CPUSYS_TOP_BASE + 0x22a0)
22 #define MP_CPUSYS_TOP_CPU_PLLDIV_CFG1 (MP_CPUSYS_TOP_BASE + 0x22a4)
23 #define MP_CPUSYS_TOP_BUS_PLLDIV_CFG (MP_CPUSYS_TOP_BASE + 0x22e0)
24 #define MP_CPUSYS_TOP_MCSIC_DCM0 (MP_CPUSYS_TOP_BASE + 0x2440)
25 #define MP_CPUSYS_TOP_MP_ADB_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2500)
26 #define MP_CPUSYS_TOP_MP_ADB_DCM_CFG4 (MP_CPUSYS_TOP_BASE + 0x2510)
27 #define MP_CPUSYS_TOP_MP_MISC_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2518)
28 #define MP_CPUSYS_TOP_MCUSYS_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x25c0)
29 #define MP_CPUSYS_TOP_MP0_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x4880)
[all …]
/trusted-firmware-a-latest/plat/mediatek/mt8186/drivers/dcm/
Dmtk_dcm_utils.h16 #define MP_CPUSYS_TOP_BASE 0xc538000 macro
21 #define MP_CPUSYS_TOP_BUS_PLLDIV_CFG (MP_CPUSYS_TOP_BASE + 0x22e0)
22 #define MP_CPUSYS_TOP_CPU_PLLDIV_CFG0 (MP_CPUSYS_TOP_BASE + 0x22a0)
23 #define MP_CPUSYS_TOP_CPU_PLLDIV_CFG1 (MP_CPUSYS_TOP_BASE + 0x22a4)
24 #define MP_CPUSYS_TOP_MCSIC_DCM0 (MP_CPUSYS_TOP_BASE + 0x2440)
25 #define MP_CPUSYS_TOP_MCSI_CFG2 (MP_CPUSYS_TOP_BASE + 0x2418)
26 #define MP_CPUSYS_TOP_MCUSYS_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x25c0)
27 #define MP_CPUSYS_TOP_MP0_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x4880)
28 #define MP_CPUSYS_TOP_MP0_DCM_CFG7 (MP_CPUSYS_TOP_BASE + 0x489c)
29 #define MP_CPUSYS_TOP_MP_ADB_DCM_CFG4 (MP_CPUSYS_TOP_BASE + 0x2510)
[all …]