Searched refs:MPIDR_MT_MASK (Results 1 – 25 of 25) sorted by relevance
26 assert((read_mpidr_el1() & MPIDR_MT_MASK) != 0); in plat_core_pos_by_mpidr()32 mpidr |= MPIDR_MT_MASK; in plat_core_pos_by_mpidr()
45 if (read_mpidr() & MPIDR_MT_MASK) { in plat_core_pos_by_mpidr()
40 if ((read_mpidr() & MPIDR_MT_MASK) != 0) { in plat_core_pos_by_mpidr()
59 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); in plat_core_pos_by_mpidr()
35 tst x0, #MPIDR_MT_MASK
38 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); in brcm_gicv3_mpidr_hash()
37 tst x1, #MPIDR_MT_MASK
60 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); in marvell_gicv3_mpidr_hash()
60 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); in versal_gicv3_mpidr_hash()
61 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); in versal_net_gicv3_mpidr_hash()
121 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); in plat_core_pos_by_mpidr()
59 temp_mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); in fvp_gicv3_mpidr_hash()
405 if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U) in fvp_config_setup()
37 and x1, x1, #MPIDR_MT_MASK
111 tst r0, #MPIDR_MT_MASK
128 tst r0, #MPIDR_MT_MASK
78 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); in DEFINE_LOAD_SYM_ADDR()
162 tst x0, #MPIDR_MT_MASK
63 if ((mpidr & MPIDR_MT_MASK) == 0) { /* MT not supported */ in plat_qti_my_cluster_pos()
135 tst x0, #MPIDR_MT_MASK
253 reg_prop = mpidr & MPID_MASK & ~MPIDR_MT_MASK; in fdt_add_cpu()377 (read_mpidr_el1() & MPIDR_MT_MASK); in fdt_add_cpus_node()
190 if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U) { in fvp_config_setup()
29 #define MPIDR_MT_MASK (U(1) << 24) macro56 #define MPID_MASK (MPIDR_MT_MASK |\
30 #define MPIDR_MT_MASK (ULL(1) << 24) macro62 #define MPID_MASK (MPIDR_MT_MASK | \
