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Searched refs:MPIDR_AFFLVL2 (Results 1 – 25 of 43) sorted by relevance

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/trusted-firmware-a-latest/plat/rockchip/rk3288/include/
Dplatform_def.h38 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
50 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
/trusted-firmware-a-latest/plat/rockchip/rk3328/include/
Dplatform_def.h38 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
50 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
/trusted-firmware-a-latest/plat/rockchip/rk3399/include/
Dplatform_def.h40 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
52 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
/trusted-firmware-a-latest/plat/rockchip/px30/include/
Dplatform_def.h41 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
53 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
/trusted-firmware-a-latest/plat/rockchip/rk3368/include/
Dplatform_def.h39 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
53 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
/trusted-firmware-a-latest/plat/hisilicon/hikey/include/
Dplatform_def.h35 #define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL2)
/trusted-firmware-a-latest/plat/amlogic/axg/include/
Dplatform_def.h27 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
/trusted-firmware-a-latest/plat/qti/msm8916/include/
Dplatform_def.h48 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
/trusted-firmware-a-latest/plat/imx/imx8qm/include/
Dplatform_def.h28 #define IMX_PWR_LVL2 MPIDR_AFFLVL2
/trusted-firmware-a-latest/plat/nxp/soc-ls1046a/include/
Dsoc.h95 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
/trusted-firmware-a-latest/plat/qti/sc7180/inc/
Dplatform_def.h33 #define QTI_PWR_LVL2 MPIDR_AFFLVL2
/trusted-firmware-a-latest/plat/qti/sc7280/inc/
Dplatform_def.h33 #define QTI_PWR_LVL2 MPIDR_AFFLVL2
/trusted-firmware-a-latest/plat/hisilicon/hikey960/include/
Dplatform_def.h32 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
/trusted-firmware-a-latest/plat/arm/board/arm_fpga/include/
Dplatform_def.h82 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
/trusted-firmware-a-latest/plat/nxp/soc-lx2160a/include/
Dsoc.h126 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
/trusted-firmware-a-latest/plat/nvidia/tegra/include/
Dplatform_def.h44 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
/trusted-firmware-a-latest/plat/nxp/soc-ls1028a/include/
Dsoc.h121 #define PLAT_PD_COORD_LVL MPIDR_AFFLVL2
/trusted-firmware-a-latest/include/plat/marvell/armada/a3k/common/
Dmarvell_def.h37 #define MARVELL_PWR_LVL2 MPIDR_AFFLVL2
/trusted-firmware-a-latest/plat/mediatek/mt8173/include/
Dplatform_def.h39 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
/trusted-firmware-a-latest/include/plat/marvell/armada/a8k/common/
Dmarvell_def.h34 #define MARVELL_PWR_LVL2 MPIDR_AFFLVL2
/trusted-firmware-a-latest/plat/ti/k3/include/
Dplatform_def.h40 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
/trusted-firmware-a-latest/plat/nxp/soc-ls1088a/include/
Dsoc.h203 #define PLAT_PD_COORD_LVL MPIDR_AFFLVL2
/trusted-firmware-a-latest/plat/nvidia/tegra/soc/t210/
Dplat_psci_handlers.c114 if (lvl == MPIDR_AFFLVL2) in tegra_soc_get_target_pwr_state()
175 } else if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) && in tegra_soc_get_target_pwr_state()
199 unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2]; in tegra_soc_pwr_domain_suspend()
/trusted-firmware-a-latest/plat/nxp/soc-ls1043a/include/
Dsoc.h199 #define PLAT_PD_COORD_LVL MPIDR_AFFLVL2
/trusted-firmware-a-latest/plat/amlogic/axg/
Daxg_pm.c124 if (target_state->pwr_domain_state[MPIDR_AFFLVL2] == in axg_pwr_domain_off()

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