Searched refs:IMX_SRC_BASE (Results 1 – 11 of 11) sorted by relevance
| /trusted-firmware-a-latest/plat/imx/imx8m/imx8mm/ |
| D | gpc.c | 160 mmio_write_32(IMX_SRC_BASE + GPU_RCR, 0x1); in imx_gpc_pm_domain_enable()
186 mmio_write_32(IMX_SRC_BASE + GPU_RCR, 0x0); in imx_gpc_pm_domain_enable()
192 mmio_write_32(IMX_SRC_BASE + VPU_RCR, 0x1); in imx_gpc_pm_domain_enable()
194 mmio_write_32(IMX_SRC_BASE + VPU_RCR, 0x0); in imx_gpc_pm_domain_enable()
373 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); in imx_gpc_init()
374 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1); in imx_gpc_init()
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| /trusted-firmware-a-latest/plat/imx/imx8m/ |
| D | gpc_common.c | 44 mmio_write_32(IMX_SRC_BASE + SRC_GPR1_OFFSET + (core_id << 3), in imx_set_cpu_secure_entry()
46 mmio_write_32(IMX_SRC_BASE + SRC_GPR1_OFFSET + (core_id << 3) + 4, in imx_set_cpu_secure_entry()
74 mmio_clrbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id)); in imx_set_cpu_pwr_on()
87 mmio_setbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id)); in imx_set_cpu_pwr_on()
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| /trusted-firmware-a-latest/plat/imx/common/ |
| D | imx_sip_handler.c | 161 mmio_setbits_32(IMX_SRC_BASE + SRC_GPR10_OFFSET, in imx_src_handler()
164 mmio_clrbits_32(IMX_SRC_BASE + SRC_GPR10_OFFSET, in imx_src_handler()
169 val = mmio_read_32(IMX_SRC_BASE + SRC_GPR10_OFFSET); in imx_src_handler()
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| /trusted-firmware-a-latest/plat/imx/imx8m/ddr/ |
| D | dram_retention.c | 14 #define SRC_DDR1_RCR (IMX_SRC_BASE + 0x1000)
15 #define SRC_DDR2_RCR (IMX_SRC_BASE + 0x1004)
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| /trusted-firmware-a-latest/plat/imx/imx8m/imx8mp/ |
| D | gpc.c | 216 while (!(mmio_read_32(IMX_SRC_BASE + 0x94) & BIT(8))) in imx_gpc_pm_domain_enable()
374 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); in imx_gpc_init()
375 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1); in imx_gpc_init()
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| /trusted-firmware-a-latest/plat/imx/imx8m/imx8mq/include/ |
| D | platform_def.h | 73 #define IMX_SRC_BASE U(0x30390000) macro
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| /trusted-firmware-a-latest/plat/imx/imx8m/imx8mn/ |
| D | gpc.c | 206 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); in imx_gpc_init()
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| /trusted-firmware-a-latest/plat/imx/imx8m/imx8mq/ |
| D | gpc.c | 436 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); in imx_gpc_init()
437 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1); in imx_gpc_init()
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| /trusted-firmware-a-latest/plat/imx/imx8m/imx8mm/include/ |
| D | platform_def.h | 99 #define IMX_SRC_BASE U(0x30390000) macro
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| /trusted-firmware-a-latest/plat/imx/imx8m/imx8mn/include/ |
| D | platform_def.h | 82 #define IMX_SRC_BASE U(0x30390000) macro
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| /trusted-firmware-a-latest/plat/imx/imx8m/imx8mp/include/ |
| D | platform_def.h | 101 #define IMX_SRC_BASE U(0x30390000) macro
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