Searched refs:GPU3D_PWR_REQ (Results 1 – 3 of 3) sorted by relevance
177 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, GPU3D_PWR_REQ); in imx_gpc_pm_domain_enable()180 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & GPU3D_PWR_REQ) { in imx_gpc_pm_domain_enable()285 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, GPU3D_PWR_REQ); in imx_gpc_pm_domain_enable()288 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & GPU3D_PWR_REQ) { in imx_gpc_pm_domain_enable()
91 #define GPU3D_PWR_REQ BIT(9) macro
98 #define GPU3D_PWR_REQ BIT(9) macro
