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Searched refs:GPIO4_BASE (Results 1 – 9 of 9) sorted by relevance

/trusted-firmware-a-latest/plat/imx/imx93/
Dimx93_bl31_setup.c114 mmio_write_32(GPIO4_BASE + 0x10, 0xffffffff); in bl31_plat_arch_setup()
115 mmio_write_32(GPIO4_BASE + 0x14, 0x3); in bl31_plat_arch_setup()
116 mmio_write_32(GPIO4_BASE + 0x18, 0xffffffff); in bl31_plat_arch_setup()
117 mmio_write_32(GPIO4_BASE + 0x1c, 0x3); in bl31_plat_arch_setup()
/trusted-firmware-a-latest/plat/hisilicon/hikey/include/
Dhi6220.h60 #define GPIO4_BASE 0xF7020000 macro
/trusted-firmware-a-latest/plat/imx/imx93/include/
Dplatform_def.h61 #define GPIO4_BASE U(0x43830000) macro
/trusted-firmware-a-latest/plat/rockchip/rk3399/include/shared/
Daddressmap_shared.h42 #define GPIO4_BASE (MMIO_BASE + 0x07790000) macro
/trusted-firmware-a-latest/plat/hisilicon/hikey960/
Dhikey960_bl_common.c451 pl061_gpio_register(GPIO4_BASE, 4); in hikey960_gpio_init()
/trusted-firmware-a-latest/plat/hisilicon/hikey960/include/
Dhi3660.h247 #define GPIO4_BASE UL(0xE8A0F000) macro
/trusted-firmware-a-latest/plat/hisilicon/hikey/
Dhikey_bl_common.c57 pl061_gpio_register(GPIO4_BASE, 4); in hikey_gpio_init()
/trusted-firmware-a-latest/plat/rockchip/rk3399/drivers/pmu/
Dpmu.c939 gpio_direction[2] = mmio_read_32(GPIO4_BASE + 0x04); in suspend_apio()
1009 mmio_clrbits_32(GPIO4_BASE + 0x04, 0x7fff0000); in suspend_apio()
1026 mmio_clrbits_32(GPIO4_BASE + 0x04, 0x000000ff); in suspend_apio()
1050 mmio_write_32(GPIO4_BASE + 0x04, gpio_direction[2]); in resume_apio()
/trusted-firmware-a-latest/plat/rockchip/rk3399/drivers/gpio/
Drk3399_gpio.c109 .port_base = GPIO4_BASE,