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Searched refs:ECC (Results 1 – 15 of 15) sorted by relevance

/trusted-firmware-a-latest/include/drivers/nxp/crypto/caam/
Dcaam.h27 ECC enumerator
/trusted-firmware-a-latest/drivers/nxp/crypto/caam/src/auth/
Dnxp_crypto.c56 case ECC: in verify_signature()
/trusted-firmware-a-latest/plat/nxp/soc-ls1088a/
Dsoc.def85 # OCRAM ECC Enabled
/trusted-firmware-a-latest/plat/nxp/soc-ls1028a/
Dsoc.def96 # OCRAM ECC Enabled
/trusted-firmware-a-latest/plat/nxp/soc-ls1046a/
Dsoc.def106 # OCRAM ECC Enabled
/trusted-firmware-a-latest/plat/nxp/soc-ls1043a/
Dsoc.def106 # OCRAM ECC Enabled
/trusted-firmware-a-latest/docs/plat/
Dintel-agilex.rst72 INFO: ECC is disabled.
Dintel-stratix10.rst72 INFO: ECC is disabled.
Dnvidia-tegra.rst129 /* L2 ECC parity protection disable flag \*/
146 - 'tegra\_enable\_l2\_ecc\_parity\_prot': This flag enables the L2 ECC and Parity
/trusted-firmware-a-latest/plat/nxp/soc-lx2160a/
Dsoc.def118 # OCRAM ECC Enabled
/trusted-firmware-a-latest/docs/components/
Drmm-el3-comms-spec.rst430 Supported ECC Curves
437 0,ECC SECP384R1
/trusted-firmware-a-latest/docs/plat/nxp/
Dnxp-layerscape.rst103 Arm Cortex-A72 cores with ECC-protected L1 and L2 cache memories for high
/trusted-firmware-a-latest/docs/plat/marvell/armada/
Dbuild.rst395 In order to work in 32bit DDR, instead of the default 64bit ECC DDR,
/trusted-firmware-a-latest/docs/
Dchange-log.md1938 …- enable OCRAM ECC ([e8faff3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firm…
1979 …- set L2 cache ECC and and parity on A72 cores ([81858a3](https://review.trustedfirmware.org/plugi…
3844 …- fix ECC Double Bit Error handling ([c703d75](https://review.trustedfirmware.org/plugins/gitiles/…
5934 - Added support for DDR with 32-bit bus width (both ECC and non-ECC)
6709 - arm/n1sdp: Add code for DDR ECC enablement and BL33 copy to DDR, Initialise
Dporting-guide.rst2256 sign Realm attestation token. The API currently only supports P-384 ECC curve