Searched refs:DRAM_BASE (Results 1 – 17 of 17) sorted by relevance
| /trusted-firmware-a-latest/plat/imx/imx7/picopi/include/ |
| D | platform_def.h | 70 #define DRAM_BASE 0x80000000 macro
72 #define DRAM_LIMIT (DRAM_BASE + DRAM_SIZE)
91 #define IMX7_UBOOT_BASE (DRAM_BASE + 0x7800000)
96 #define IMX_FIP_BASE (DRAM_BASE)
104 #define IMX7_DTB_BASE (DRAM_BASE + 0x03000000)
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| /trusted-firmware-a-latest/plat/imx/imx7/warp7/include/ |
| D | platform_def.h | 72 #define DRAM_BASE 0x80000000 macro
74 #define DRAM_LIMIT (DRAM_BASE + DRAM_SIZE)
93 #define IMX7_UBOOT_BASE (DRAM_BASE + 0x7800000)
98 #define IMX_FIP_BASE (DRAM_BASE)
106 #define IMX7_DTB_BASE (DRAM_BASE + 0x03000000)
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| /trusted-firmware-a-latest/plat/intel/soc/stratix10/include/ |
| D | socfpga_plat_def.h | 45 #define DRAM_BASE (0x0) macro
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| /trusted-firmware-a-latest/plat/intel/soc/agilex/include/ |
| D | socfpga_plat_def.h | 46 #define DRAM_BASE (0x0) macro
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| /trusted-firmware-a-latest/plat/intel/soc/n5x/include/ |
| D | socfpga_plat_def.h | 47 #define DRAM_BASE (0x0) macro
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| /trusted-firmware-a-latest/plat/intel/soc/agilex5/include/ |
| D | socfpga_plat_def.h | 60 #define DRAM_BASE (0x80000000) macro
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| /trusted-firmware-a-latest/plat/intel/soc/agilex5/ |
| D | bl2_plat_setup.c | 47 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
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| D | bl31_plat_setup.c | 177 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
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| /trusted-firmware-a-latest/plat/intel/soc/agilex/ |
| D | bl2_plat_setup.c | 37 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
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| D | bl31_plat_setup.c | 144 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
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| /trusted-firmware-a-latest/plat/intel/soc/stratix10/ |
| D | bl2_plat_setup.c | 36 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
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| D | bl31_plat_setup.c | 131 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
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| /trusted-firmware-a-latest/plat/intel/soc/n5x/ |
| D | bl31_plat_setup.c | 124 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
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| /trusted-firmware-a-latest/plat/intel/soc/agilex/soc/ |
| D | agilex_memory_controller.c | 395 zeromem(DRAM_BASE, DRAM_SIZE); in configure_hmc_adaptor_regs()
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| /trusted-firmware-a-latest/plat/intel/soc/agilex5/soc/ |
| D | agilex5_memory_controller.c | 396 zeromem((void *)DRAM_BASE, DRAM_SIZE); in configure_hmc_adaptor_regs()
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| /trusted-firmware-a-latest/plat/intel/soc/stratix10/soc/ |
| D | s10_memory_controller.c | 407 zeromem(DRAM_BASE, DRAM_SIZE); in configure_hmc_adaptor_regs()
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| /trusted-firmware-a-latest/plat/intel/soc/common/ |
| D | socfpga_sip_svc.c | 292 if (addr + size > DRAM_BASE + DRAM_SIZE) { in is_address_in_ddr_range()
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