| /trusted-firmware-a-latest/lib/cpus/aarch64/ |
| D | wa_cve_2022_23960_bhb.S | 16 str x2, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
28 ldr x2, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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| D | wa_cve_2017_5715_bpiall.S | 27 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
342 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
346 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
350 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
366 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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| D | cortex_a76.S | 45 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
67 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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| D | neoverse_n1.S | 265 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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| /trusted-firmware-a-latest/plat/nvidia/tegra/soc/t186/drivers/mce/ |
| D | mce.c | 210 write_ctx_reg(gp_regs, CTX_GPREG_X2, (ret64)); in mce_command_handler()
253 write_ctx_reg(gp_regs, CTX_GPREG_X2, ((ret64 == arg0) ? in mce_command_handler()
267 write_ctx_reg(gp_regs, CTX_GPREG_X2, (ret64 >> 32ULL)); in mce_command_handler()
300 write_ctx_reg(gp_regs, CTX_GPREG_X2, (arg1)); in mce_command_handler()
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| /trusted-firmware-a-latest/plat/nvidia/tegra/soc/t194/ |
| D | plat_sip_calls.c | 69 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2, per[1]); in plat_sip_handler()
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| /trusted-firmware-a-latest/services/std_svc/spm/el3_spmc/ |
| D | spmc_pm.c | 33 write_ctx_reg(gpregs, CTX_GPREG_X2, FFA_FWK_MSG_BIT | in spmc_build_pm_message()
171 resp = read_ctx_reg(gpregs_ctx, CTX_GPREG_X2); in spmc_send_pm_msg()
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| D | spmc_main.c | 296 uint64_t x2 = SMC_GET_GP(handle, CTX_GPREG_X2); in direct_msg_validate_lp_resp()
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| /trusted-firmware-a-latest/plat/nvidia/tegra/common/ |
| D | tegra_fiq_glue.c | 143 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X2), (val)); in tegra_fiq_get_intr_context()
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| /trusted-firmware-a-latest/plat/nvidia/tegra/soc/t186/ |
| D | plat_sip_calls.c | 148 CTX_GPREG_X2, (ref_clk_ctr)); in plat_sip_handler()
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| /trusted-firmware-a-latest/include/arch/aarch64/ |
| D | smccc_helpers.h | 45 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X2), (_x2)); \
112 _x2 = read_ctx_reg(regs, CTX_GPREG_X2); \
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| /trusted-firmware-a-latest/services/std_svc/spmd/ |
| D | spmd_logical_sp.c | 145 write_ctx_reg(gpregs, CTX_GPREG_X2, x2); in spmd_build_direct_message_req()
160 retval->arg2 = read_ctx_reg(gpregs, CTX_GPREG_X2); in spmd_encode_ctx_to_ffa_value()
201 write_ctx_reg(gpregs, CTX_GPREG_X2, arg2); in spmd_build_ffa_info_get_regs()
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| D | spmd_main.c | 111 write_ctx_reg(gpregs, CTX_GPREG_X2, BIT(31) | target_func); in spmd_build_spmc_message()
238 write_ctx_reg(gpregs, CTX_GPREG_X2, 0); in spmd_secure_interrupt_handler()
974 (SMC_GET_GP(gpregs, CTX_GPREG_X2) != in spmd_smc_handler()
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| /trusted-firmware-a-latest/services/std_svc/spm/spm_mm/ |
| D | spm_mm_main.c | 209 write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X2, x2); in spm_mm_sp_call()
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| /trusted-firmware-a-latest/include/lib/el3_runtime/aarch64/ |
| D | context.h | 20 #define CTX_GPREG_X2 U(0x10) macro
522 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \
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| /trusted-firmware-a-latest/bl31/aarch64/ |
| D | runtime_exceptions.S | 608 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
627 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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| /trusted-firmware-a-latest/plat/qti/qtiseclib/src/ |
| D | qtiseclib_cb_interface.c | 152 qti_ns_ctx->x2 = read_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2); in qtiseclib_cb_get_ns_ctx()
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| /trusted-firmware-a-latest/lib/el3_runtime/aarch64/ |
| D | context.S | 406 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
512 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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| /trusted-firmware-a-latest/docs/security_advisories/ |
| D | security-advisory-tfv-8.rst | 50 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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| /trusted-firmware-a-latest/services/std_svc/sdei/ |
| D | sdei_intr_mgmt.c | 330 SMC_SET_GP(ctx, CTX_GPREG_X2, disp_ctx->elr_el3); in setup_ns_dispatch()
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