1 /* 2 * Copyright 2020-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef IMX_SEC_DEF_H 8 #define IMX_SEC_DEF_H 9 10 /* RDC MDA index */ 11 enum rdc_mda_idx { 12 RDC_MDA_A53 = 0, 13 RDC_MDA_M4 = 1, 14 RDC_MDA_PCIE_CTRL1 = 2, 15 RDC_MDA_PCIE_CTRL2 = 3, 16 RDC_MDA_VPU_DEC = 4, 17 RDC_MDA_LCDIF = 5, 18 RDC_MDA_CSI1 = 6, 19 RDC_MDA_CSI2 = 7, 20 RDC_MDA_Coresight = 8, 21 RDC_MDA_DAP = 9, 22 RDC_MDA_CAAM = 10, 23 RDC_MDA_SDMAp = 11, 24 RDC_MDA_SDMAb = 12, 25 RDC_MDA_APBHDMA = 13, 26 RDC_MDA_RAWNAND = 14, 27 RDC_MDA_uSDHC1 = 15, 28 RDC_MDA_uSDHC2 = 16, 29 RDC_MDA_DCSS = 17, 30 RDC_MDA_GPU = 18, 31 RDC_MDA_USB1 = 19, 32 RDC_MDA_USB2 = 20, 33 RDC_MDA_TESTPORT = 21, 34 RDC_MDA_ENET1_TX = 22, 35 RDC_MDA_ENET1_RX = 23, 36 RDC_MDA_SDMA2 = 24, 37 RDC_MDA_SDMA1 = 26, 38 }; 39 40 /* RDC Peripherals index */ 41 enum rdc_pdap_idx { 42 RDC_PDAP_GPIO1 = 0, 43 RDC_PDAP_GPIO2 = 1, 44 RDC_PDAP_GPIO3 = 2, 45 RDC_PDAP_GPIO4 = 3, 46 RDC_PDAP_GPIO5 = 4, 47 RDC_PDAP_ANA_TSENSOR = 6, 48 RDC_PDAP_ANA_OSC = 7, 49 RDC_PDAP_WDOG1 = 8, 50 RDC_PDAP_WDOG2 = 9, 51 RDC_PDAP_WDOG3 = 10, 52 RDC_PDAP_SDMA2 = 12, 53 RDC_PDAP_GPT1 = 13, 54 RDC_PDAP_GPT2 = 14, 55 RDC_PDAP_GPT3 = 15, 56 RDC_PDAP_ROMCP = 17, 57 RDC_PDAP_LCDIF = 18, 58 RDC_PDAP_IOMUXC = 19, 59 RDC_PDAP_IOMUXC_GPR = 20, 60 RDC_PDAP_OCOTP_CTRL = 21, 61 RDC_PDAP_ANATOP_PLL = 22, 62 RDC_PDAP_SNVS_HP = 23, 63 RDC_PDAP_CCM = 24, 64 RDC_PDAP_SRC = 25, 65 RDC_PDAP_GPC = 26, 66 RDC_PDAP_SEMAPHORE1 = 27, 67 RDC_PDAP_SEMAPHORE2 = 28, 68 RDC_PDAP_RDC = 29, 69 RDC_PDAP_CSU = 30, 70 RDC_PDAP_MST0 = 32, 71 RDC_PDAP_MST1 = 33, 72 RDC_PDAP_MST2 = 34, 73 RDC_PDAP_MST3 = 35, 74 RDC_PDAP_HDMI_SEC = 36, 75 RDC_PDAP_PWM1 = 38, 76 RDC_PDAP_PWM2 = 39, 77 RDC_PDAP_PWM3 = 40, 78 RDC_PDAP_PWM4 = 41, 79 RDC_PDAP_SysCounter_RD = 42, 80 RDC_PDAP_SysCounter_CMP = 43, 81 RDC_PDAP_SysCounter_CTRL = 44, 82 RDC_PDAP_HDMI_CTRL = 45, 83 RDC_PDAP_GPT6 = 46, 84 RDC_PDAP_GPT5 = 47, 85 RDC_PDAP_GPT4 = 48, 86 RDC_PDAP_TZASC = 56, 87 RDC_PDAP_MTR = 59, 88 RDC_PDAP_PERFMON1 = 60, 89 RDC_PDAP_PERFMON2 = 61, 90 RDC_PDAP_PLATFORM_CTRL = 62, 91 RDC_PDAP_QoSC = 63, 92 RDC_PDAP_MIPI_PHY = 64, 93 RDC_PDAP_MIPI_DSI = 65, 94 RDC_PDAP_I2C1 = 66, 95 RDC_PDAP_I2C2 = 67, 96 RDC_PDAP_I2C3 = 68, 97 RDC_PDAP_I2C4 = 69, 98 RDC_PDAP_UART4 = 70, 99 RDC_PDAP_MIPI_CSI1 = 71, 100 RDC_PDAP_MIPI_CSI_PHY1 = 72, 101 RDC_PDAP_CSI1 = 73, 102 RDC_PDAP_MU_A = 74, 103 RDC_PDAP_MU_B = 75, 104 RDC_PDAP_SEMAPHORE_HS = 76, 105 RDC_PDAP_SAI1 = 78, 106 RDC_PDAP_SAI6 = 80, 107 RDC_PDAP_SAI5 = 81, 108 RDC_PDAP_SAI4 = 82, 109 RDC_PDAP_USDHC1 = 84, 110 RDC_PDAP_USDHC2 = 85, 111 RDC_PDAP_MIPI_CSI2 = 86, 112 RDC_PDAP_MIPI_CSI_PHY2 = 87, 113 RDC_PDAP_CSI2 = 88, 114 RDC_PDAP_QSPI = 91, 115 RDC_PDAP_SDMA1 = 93, 116 RDC_PDAP_ENET1 = 94, 117 RDC_PDAP_SPDIF1 = 97, 118 RDC_PDAP_ECSPI1 = 98, 119 RDC_PDAP_ECSPI2 = 99, 120 RDC_PDAP_ECSPI3 = 100, 121 RDC_PDAP_UART1 = 102, 122 RDC_PDAP_UART3 = 104, 123 RDC_PDAP_UART2 = 105, 124 RDC_PDAP_SPDIF2 = 106, 125 RDC_PDAP_SAI2 = 107, 126 RDC_PDAP_SAI3 = 108, 127 RDC_PDAP_SPBA1 = 111, 128 RDC_PDAP_CAAM = 114, 129 RDC_PDAP_DDRC_SEC = 115, 130 RDC_PDAP_GIC_EXSC = 116, 131 RDC_PDAP_USB_EXSC = 117, 132 RDC_PDAP_OCRAM_TZ = 118, 133 RDC_PDAP_OCRAM_S_TZ = 119, 134 RDC_PDAP_VPU_SEC = 120, 135 RDC_PDAP_DAP_EXSC = 121, 136 RDC_PDAP_ROMCP_SEC = 122, 137 RDC_PDAP_APBHDMA_SEC = 123, 138 RDC_PDAP_M4_SEC = 124, 139 RDC_PDAP_QSPI_SEC = 125, 140 RDC_PDAP_GPU_EXSC = 126, 141 RDC_PDAP_PCIE = 127, 142 }; 143 144 enum csu_csl_idx { 145 CSU_CSL_GPIO1 = 0, 146 CSU_CSL_GPIO2 = 1, 147 CSU_CSL_GPIO3 = 2, 148 CSU_CSL_GPIO4 = 3, 149 CSU_CSL_GPIO5 = 4, 150 CSU_CSL_ANA_TSENSOR = 6, 151 CSU_CSL_ANA_OSC = 7, 152 CSU_CSL_WDOG1 = 8, 153 CSU_CSL_WDOG2 = 9, 154 CSU_CSL_WDOG3 = 10, 155 CSU_CSL_SDMA2 = 12, 156 CSU_CSL_GPT1 = 13, 157 CSU_CSL_GPT2 = 14, 158 CSU_CSL_GPT3 = 15, 159 CSU_CSL_ROMCP = 17, 160 CSU_CSL_LCDIF = 18, 161 CSU_CSL_IOMUXC = 19, 162 CSU_CSL_IOMUXC_GPR = 20, 163 CSU_CSL_OCOTP_CTRL = 21, 164 CSU_CSL_ANATOP_PLL = 22, 165 CSU_CSL_SNVS_HP = 23, 166 CSU_CSL_CCM = 24, 167 CSU_CSL_SRC = 25, 168 CSU_CSL_GPC = 26, 169 CSU_CSL_SEMAPHORE1 = 27, 170 CSU_CSL_SEMAPHORE2 = 28, 171 CSU_CSL_RDC = 29, 172 CSU_CSL_CSU = 30, 173 CSU_CSL_MST0 = 32, 174 CSU_CSL_MST1 = 33, 175 CSU_CSL_MST2 = 34, 176 CSU_CSL_MST3 = 35, 177 CSU_CSL_HDMI_SEC = 36, 178 CSU_CSL_PWM1 = 38, 179 CSU_CSL_PWM2 = 39, 180 CSU_CSL_PWM3 = 40, 181 CSU_CSL_PWM4 = 41, 182 CSU_CSL_SysCounter_RD = 42, 183 CSU_CSL_SysCounter_CMP = 43, 184 CSU_CSL_SysCounter_CTRL = 44, 185 CSU_CSL_HDMI_CTRL = 45, 186 CSU_CSL_GPT6 = 46, 187 CSU_CSL_GPT5 = 47, 188 CSU_CSL_GPT4 = 48, 189 CSU_CSL_TZASC = 56, 190 CSU_CSL_MTR = 59, 191 CSU_CSL_PERFMON1 = 60, 192 CSU_CSL_PERFMON2 = 61, 193 CSU_CSL_PLATFORM_CTRL = 62, 194 CSU_CSL_QoSC = 63, 195 CSU_CSL_MIPI_PHY = 64, 196 CSU_CSL_MIPI_DSI = 65, 197 CSU_CSL_I2C1 = 66, 198 CSU_CSL_I2C2 = 67, 199 CSU_CSL_I2C3 = 68, 200 CSU_CSL_I2C4 = 69, 201 CSU_CSL_UART4 = 70, 202 CSU_CSL_MIPI_CSI1 = 71, 203 CSU_CSL_MIPI_CSI_PHY1 = 72, 204 CSU_CSL_CSI1 = 73, 205 CSU_CSL_MU_A = 74, 206 CSU_CSL_MU_B = 75, 207 CSU_CSL_SEMAPHORE_HS = 76, 208 CSU_CSL_SAI1 = 78, 209 CSU_CSL_SAI6 = 80, 210 CSU_CSL_SAI5 = 81, 211 CSU_CSL_SAI4 = 82, 212 CSU_CSL_USDHC1 = 84, 213 CSU_CSL_USDHC2 = 85, 214 CSU_CSL_MIPI_CSI2 = 86, 215 CSU_CSL_MIPI_CSI_PHY2 = 87, 216 CSU_CSL_CSI2 = 88, 217 CSU_CSL_QSPI = 91, 218 CSU_CSL_SDMA1 = 93, 219 CSU_CSL_ENET1 = 94, 220 CSU_CSL_SPDIF1 = 97, 221 CSU_CSL_ECSPI1 = 98, 222 CSU_CSL_ECSPI2 = 99, 223 CSU_CSL_ECSPI3 = 100, 224 CSU_CSL_UART1 = 102, 225 CSU_CSL_UART3 = 104, 226 CSU_CSL_UART2 = 105, 227 CSU_CSL_SPDIF2 = 106, 228 CSU_CSL_SAI2 = 107, 229 CSU_CSL_SAI3 = 108, 230 CSU_CSL_SPBA1 = 111, 231 CSU_CSL_MOD_EN3 = 112, 232 CSU_CSL_MOD_EN0 = 113, 233 CSU_CSL_CAAM = 114, 234 CSU_CSL_DDRC_SEC = 115, 235 CSU_CSL_GIC_EXSC = 116, 236 CSU_CSL_USB_EXSC = 117, 237 CSU_CSL_OCRAM_TZ = 118, 238 CSU_CSL_OCRAM_S_TZ = 119, 239 CSU_CSL_VPU_SEC = 120, 240 CSU_CSL_DAP_EXSC = 121, 241 CSU_CSL_ROMCP_SEC = 122, 242 CSU_CSL_APBHDMA_SEC = 123, 243 CSU_CSL_M4_SEC = 124, 244 CSU_CSL_QSPI_SEC = 125, 245 CSU_CSL_GPU_EXSC = 126, 246 CSU_CSL_PCIE = 127, 247 }; 248 249 #endif /* IMX_SEC_DEF_H */ 250
