Searched refs:CPU0 (Results 1 – 17 of 17) sorted by relevance
| /trusted-firmware-a-latest/plat/intel/soc/common/soc/ |
| D | socfpga_firewall.c | 120 mmio_clrbits_32(SOCFPGA_CCU_NOC(CPU0, RAM0), in enable_ns_ocram_access()
134 mmio_setbits_32(SOCFPGA_CCU_NOC(CPU0, RAM0), in enable_ocram_firewall()
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| /trusted-firmware-a-latest/fdts/ |
| D | morello-fvp.dts | 61 cpu = <&CPU0>;
76 CPU0: cpu0@0 { label
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| D | tc.dts | 30 cpu = <&CPU0>;
106 CPU0:cpu@0 { label
557 cpu = <&CPU0>;
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| D | fvp-defs.dtsi | 53 CPU0:cpu@0 { \ label
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| /trusted-firmware-a-latest/docs/plat/ |
| D | meson-axg.rst | 11 - Basic PSCI support (CPU_ON, CPU_OFF, SYSTEM_RESET, SYSTEM_OFF). Note that CPU0
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| D | meson-g12a.rst | 11 - Basic PSCI support (CPU_ON, CPU_OFF, SYSTEM_RESET, SYSTEM_OFF). Note that CPU0
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| D | meson-gxbb.rst | 11 - Basic PSCI support (CPU_ON, CPU_OFF, SYSTEM_RESET, SYSTEM_OFF). Note that CPU0
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| D | meson-gxl.rst | 11 - Basic PSCI support (CPU_ON, CPU_OFF, SYSTEM_RESET, SYSTEM_OFF). Note that CPU0
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| D | poplar.rst | 116 LOADER: CPU0 executes at 0x000ce000
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| /trusted-firmware-a-latest/plat/arm/board/tc/fdts/ |
| D | tc_spmc_manifest.dts | 59 CPU0:cpu@0 { label
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| D | tc_spmc_optee_sp_manifest.dts | 58 CPU0:cpu@0 { label
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| /trusted-firmware-a-latest/plat/marvell/armada/a8k/common/ |
| D | plat_pm.c | 68 CPU0, enumerator
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| /trusted-firmware-a-latest/docs/design/ |
| D | psci-pd-tree.rst | 248 CPU0 | 3 | |
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| D | firmware-design.rst | 2254 CPU0 updates its per-CPU field with data cache enabled. This write updates a
2259 the update made by CPU0 as well.
2296 | Lock_0 | for CPU0
2299 | Lock_1 | for CPU0
2304 | Lock_N | for CPU0
2329 operation on Lock_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1
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| /trusted-firmware-a-latest/docs/design_documents/ |
| D | psci_osi_mode.rst | 481 CPU0: cpu@0 {
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| /trusted-firmware-a-latest/docs/ |
| D | porting-guide.rst | 2175 - Target all secure SPIs to CPU0.
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| D | change-log.md | 6591 - mediatek: mt8183: Fix AARCH64 init fail on CPU0
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