Searched refs:CLR (Results 1 – 2 of 2) sorted by relevance
| /trusted-firmware-a-latest/plat/mediatek/drivers/gpio/ |
| D | mtgpio_common.c | 27 #define CLR 0x8 macro
40 mmio_write_32(DIR_BASE + 0x10U * pos + CLR, 1U << bit); in mt_set_gpio_dir_chip()
71 mmio_write_32(DOUT_BASE + 0x10U * pos + CLR, 1U << bit); in mt_set_gpio_out_chip()
108 mmio_write_32(reg1 + CLR, (1U << bit)); in mt_gpio_set_spec_pull_pupd()
111 mmio_write_32(reg2 + CLR, (1U << bit)); in mt_gpio_set_spec_pull_pupd()
112 mmio_write_32((reg2 + 0x010U) + CLR, (1U << bit)); in mt_gpio_set_spec_pull_pupd()
131 mmio_write_32(reg1 + CLR, (1U << bit)); in mt_gpio_set_pull_pu_pd()
134 mmio_write_32(reg2 + CLR, (1U << bit)); in mt_gpio_set_pull_pu_pd()
138 mmio_write_32(reg1 + CLR, (1U << bit)); in mt_gpio_set_pull_pu_pd()
139 mmio_write_32(reg2 + CLR, (1U << bit)); in mt_gpio_set_pull_pu_pd()
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| /trusted-firmware-a-latest/plat/mediatek/mt8183/drivers/gpio/ |
| D | mtgpio.c | 30 #define CLR 0x8 macro
45 mmio_write_32(DIR_BASE + 0x10 * pos + CLR, 1U << bit); in mt_set_gpio_dir_chip()
75 mmio_write_32(DOUT_BASE + 0x10 * pos + CLR, 1U << bit); in mt_set_gpio_out_chip()
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