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Searched refs:CDRU_GENPLL5_CONTROL1 (Results 1 – 2 of 2) sorted by relevance

/trusted-firmware-a-latest/plat/brcm/board/stingray/src/
Dfsx.c458 mmio_setbits_32(CDRU_GENPLL5_CONTROL1, in fs4_disable_clocks()
464 mmio_setbits_32(CDRU_GENPLL5_CONTROL1, in fs4_disable_clocks()
470 mmio_setbits_32(CDRU_GENPLL5_CONTROL1, in fs4_disable_clocks()
/trusted-firmware-a-latest/plat/brcm/board/stingray/include/
Dcrmu_def.h131 #define CDRU_GENPLL5_CONTROL1 (CDRU_BASE_ADDR + 0x24c) macro