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Searched refs:ARM_NS_DRAM1_BASE (Results 1 – 12 of 12) sorted by relevance

/trusted-firmware-a-latest/plat/arm/board/fvp/
Dfvp_drtm_addr.c23 } else if ((region_start >= ARM_NS_DRAM1_BASE) && in plat_drtm_validate_ns_region()
24 (region_start < (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE)) && in plat_drtm_validate_ns_region()
25 (region_end >= ARM_NS_DRAM1_BASE) && in plat_drtm_validate_ns_region()
26 (region_end < (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) { in plat_drtm_validate_ns_region()
/trusted-firmware-a-latest/plat/nuvoton/common/
Dnuvoton_pm.c33 if ((entrypoint >= ARM_NS_DRAM1_BASE) && in arm_validate_ns_entrypoint()
34 (entrypoint < (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) { in arm_validate_ns_entrypoint()
/trusted-firmware-a-latest/plat/arm/common/
Darm_pm.c122 if ((entrypoint >= ARM_NS_DRAM1_BASE) && (entrypoint < in arm_validate_ns_entrypoint()
123 (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) { in arm_validate_ns_entrypoint()
Darm_bl1_fwu.c39 .mem_base = ARM_NS_DRAM1_BASE,
/trusted-firmware-a-latest/plat/arm/board/corstone700/common/include/
Dplatform_def.h55 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE macro
57 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
195 ARM_NS_DRAM1_BASE, \
/trusted-firmware-a-latest/plat/arm/board/fvp_ve/include/
Dplatform_def.h34 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE macro
44 #define FVP_VE_SHARED_RAM_BASE ARM_NS_DRAM1_BASE
96 ARM_NS_DRAM1_BASE, \
/trusted-firmware-a-latest/include/plat/nuvoton/common/
Dnpcm845x_arm_def.h188 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE macro
191 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
247 ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_SIZE, \
514 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE
/trusted-firmware-a-latest/plat/arm/board/corstone1000/common/include/
Dplatform_def.h108 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE macro
110 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE - 1)
304 ARM_NS_DRAM1_BASE, \
/trusted-firmware-a-latest/plat/arm/board/juno/
Djuno_ethosn_tzmp1_def.h49 { ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, \
/trusted-firmware-a-latest/include/plat/arm/common/
Dplat_arm.h47 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
60 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
84 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
Darm_def.h230 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE macro
234 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
297 ARM_NS_DRAM1_BASE, \
753 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE
/trusted-firmware-a-latest/plat/arm/board/a5ds/include/
Dplatform_def.h100 #define ARM_NS_DRAM1_BASE (ARM_DRAM1_BASE + BOOT_SIZE) macro
120 ARM_NS_DRAM1_BASE, \