Home
last modified time | relevance | path

Searched refs:ARM_DRAM2_BASE (Results 1 – 15 of 15) sorted by relevance

/trusted-firmware-a-latest/plat/arm/board/fvp/
Dfvp_drtm_addr.c28 } else if ((region_start >= ARM_DRAM2_BASE) && in plat_drtm_validate_ns_region()
29 (region_start < (ARM_DRAM2_BASE + ARM_DRAM2_SIZE)) && in plat_drtm_validate_ns_region()
30 (region_end >= ARM_DRAM2_BASE) && in plat_drtm_validate_ns_region()
31 (region_end < (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) { in plat_drtm_validate_ns_region()
/trusted-firmware-a-latest/plat/arm/board/morello/
Dmorello_bl2_setup.c44 ARM_DRAM2_BASE, ARM_DRAM2_BASE + dram2_size); in dmc_ecc_setup()
45 zero_normalmem((void *)ARM_DRAM2_BASE, dram2_size); in dmc_ecc_setup()
46 flush_dcache_range(ARM_DRAM2_BASE, dram2_size); in dmc_ecc_setup()
86 ARM_DRAM2_BASE; in dmc_ecc_setup()
/trusted-firmware-a-latest/plat/nuvoton/common/
Dnuvoton_pm.c38 if ((entrypoint >= ARM_DRAM2_BASE) && in arm_validate_ns_entrypoint()
39 (entrypoint < (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) { in arm_validate_ns_entrypoint()
/trusted-firmware-a-latest/plat/arm/board/juno/
Djuno_ethosn_tzmp1_def.h19 #define JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE (ARM_DRAM2_BASE)
20 #define JUNO_ETHOSN_FW_TZC_PROT_DRAM2_END (ARM_DRAM2_BASE + \
Djuno_security.c53 {ARM_DRAM2_BASE, ARM_DRAM2_END,
/trusted-firmware-a-latest/plat/arm/board/n1sdp/
Dn1sdp_bl2_setup.c41 zero_normalmem((void *)ARM_DRAM2_BASE, dram2_size); in dmc_ecc_setup()
42 flush_dcache_range(ARM_DRAM2_BASE, dram2_size); in dmc_ecc_setup()
/trusted-firmware-a-latest/plat/arm/common/
Darm_pm.c127 if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint < in arm_validate_ns_entrypoint()
128 (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) { in arm_validate_ns_entrypoint()
Darm_nor_psci_mem_protect.c29 {ARM_DRAM2_BASE, 1u << ONE_GB_SHIFT},
/trusted-firmware-a-latest/plat/arm/board/fvp_ve/include/
Dplatform_def.h29 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE macro
31 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \
101 ARM_DRAM2_BASE, \
/trusted-firmware-a-latest/include/plat/arm/common/
Darm_pas_def.h79 #define ARM_PAS_4_BASE ARM_DRAM2_BASE
Dplat_arm.h52 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
62 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
86 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
Darm_def.h246 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE macro
248 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \
302 ARM_DRAM2_BASE, \
/trusted-firmware-a-latest/include/plat/nuvoton/common/
Dnpcm845x_arm_def.h195 #define ARM_DRAM2_BASE 0 /* PLAT_ARM_DRAM_BASE */ macro
197 #define ARM_DRAM2_END (ARM_DRAM2_BASE + ARM_DRAM2_SIZE - 1U)
264 ARM_DRAM2_BASE, ARM_DRAM2_SIZE, \
/trusted-firmware-a-latest/plat/arm/css/sgi/include/
Dsgi_base_platform_def.h283 {CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_BASE, \
/trusted-firmware-a-latest/plat/arm/board/corstone1000/common/include/
Dplatform_def.h104 #define ARM_DRAM2_BASE ARM_DRAM1_BASE macro