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Searched refs:ARM_AP_TZC_DRAM1_BASE (Results 1 – 10 of 10) sorted by relevance

/trusted-firmware-a-latest/include/plat/arm/common/
Darm_def.h184 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ macro
195 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \
211 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \
611 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE
612 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
693 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
695 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
696 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
699 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
705 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \
[all …]
Darm_pas_def.h75 #define ARM_PAS_3_BASE (ARM_AP_TZC_DRAM1_BASE)
Dplat_arm.h45 {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\
58 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\
82 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\
/trusted-firmware-a-latest/plat/arm/css/sgi/include/
Dsgi_dmc620_tzc_regions.h15 .region_base = ARM_AP_TZC_DRAM1_BASE, \
30 .region_base = ARM_AP_TZC_DRAM1_BASE, \
/trusted-firmware-a-latest/include/plat/nuvoton/common/
Dnpcm845x_arm_def.h144 #define ARM_AP_TZC_DRAM1_BASE 0x02100000 macro
148 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \
164 #define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE
166 #define BL32_BASE ARM_AP_TZC_DRAM1_BASE
167 #define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
171 ARM_AP_TZC_DRAM1_BASE + ARM_AP_TZC_DRAM1_SIZE - \
453 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE
455 ARM_AP_TZC_DRAM1_BASE + PLAT_ARM_MAX_BL31_SIZE)
/trusted-firmware-a-latest/plat/arm/board/juno/
Djuno_tzmp1_def.h16 #define JUNO_AP_TZC_SHARE_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \
18 #define JUNO_AP_TZC_SHARE_DRAM1_END (ARM_AP_TZC_DRAM1_BASE - 1)
Djuno_ethosn_tzmp1_def.h47 { ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE, \
Djuno_security.c42 {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},
/trusted-firmware-a-latest/plat/arm/board/tc/include/
Dplatform_def.h47 #define TC_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \
/trusted-firmware-a-latest/include/plat/nuvoton/npcm845x/
Dplatform_def.h232 #pragma message(VAR_NAME_VALUE(ARM_AP_TZC_DRAM1_BASE))