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Searched refs:APU_ACC_CONFG_CLR0 (Results 1 – 4 of 4) sorted by relevance

/trusted-firmware-a-latest/plat/mediatek/mt8195/drivers/apusys/
Dapupwr_clkctl.c40 APU_ACC_CONFG_CLR0, APU_ACC_CONFG_CLR7
50 { APU_ACC_CONFG_CLR0, BIT(BIT_CGEN_SOC) },
Dapupwr_clkctl_def.h165 #define APU_ACC_CONFG_CLR0 (APU_ACC_BASE + 0x040) macro
/trusted-firmware-a-latest/plat/mediatek/drivers/apusys/mt8188/
Dapusys_power.h134 #define APU_ACC_CONFG_CLR0 (0x0040) macro
Dapusys_power.c299 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_CLR0, CGEN_SOC); in apu_acc_init()