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Searched refs:APU_ACC_BASE (Results 1 – 3 of 3) sorted by relevance

/trusted-firmware-a-latest/plat/mediatek/mt8195/drivers/apusys/
Dapupwr_clkctl_def.h157 #define APU_ACC_BASE (APUSYS_APU_ACC_BASE) macro
158 #define APU_ACC_CONFG_SET0 (APU_ACC_BASE + 0x000)
159 #define APU_ACC_CONFG_SET1 (APU_ACC_BASE + 0x004)
160 #define APU_ACC_CONFG_SET2 (APU_ACC_BASE + 0x008)
161 #define APU_ACC_CONFG_SET4 (APU_ACC_BASE + 0x010)
162 #define APU_ACC_CONFG_SET5 (APU_ACC_BASE + 0x014)
163 #define APU_ACC_CONFG_SET7 (APU_ACC_BASE + 0x01C)
165 #define APU_ACC_CONFG_CLR0 (APU_ACC_BASE + 0x040)
166 #define APU_ACC_CONFG_CLR1 (APU_ACC_BASE + 0x044)
167 #define APU_ACC_CONFG_CLR2 (APU_ACC_BASE + 0x048)
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/trusted-firmware-a-latest/plat/mediatek/drivers/apusys/mt8188/
Dapusys_power.c299 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_CLR0, CGEN_SOC); in apu_acc_init()
300 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_SET0, HW_CTRL_EN); in apu_acc_init()
302 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_CLR1, CGEN_SOC); in apu_acc_init()
303 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_SET1, HW_CTRL_EN); in apu_acc_init()
305 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_CLR2, CGEN_SOC); in apu_acc_init()
306 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_SET2, HW_CTRL_EN); in apu_acc_init()
307 mmio_write_32(APU_ACC_BASE + APU_ACC_AUTO_CTRL_SET2, CLK_REQ_SW_EN); in apu_acc_init()
309 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_CLR3, CGEN_SOC); in apu_acc_init()
310 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_SET3, HW_CTRL_EN); in apu_acc_init()
311 mmio_write_32(APU_ACC_BASE + APU_ACC_AUTO_CTRL_SET3, CLK_REQ_SW_EN); in apu_acc_init()
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Dapusys_power.h68 #define APU_ACC_BASE (APU_ACC) macro