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Searched refs:AML_PSCI_MAILBOX_BASE (Results 1 – 8 of 8) sorted by relevance

/trusted-firmware-a-latest/plat/amlogic/axg/
Daxg_pm.c32 uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4); in axg_pm_set_reset_addr()
40 uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4) + 8; in axg_pm_reset()
Daxg_def.h55 #define AML_PSCI_MAILBOX_BASE UL(0xFFFD3F00) macro
/trusted-firmware-a-latest/plat/amlogic/gxbb/
Dgxbb_pm.c33 uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4); in gxbb_program_mailbox()
134 uintptr_t addr = AML_PSCI_MAILBOX_BASE + 8 + (core << 4); in gxbb_pwr_domain_off()
Dgxbb_def.h47 #define AML_PSCI_MAILBOX_BASE UL(0xD9013F00) macro
/trusted-firmware-a-latest/plat/amlogic/g12a/
Dg12a_pm.c33 uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4); in g12a_pm_set_reset_addr()
41 uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4) + 8; in g12a_pm_reset()
Dg12a_def.h58 #define AML_PSCI_MAILBOX_BASE UL(0xFFFE7F00) macro
/trusted-firmware-a-latest/plat/amlogic/gxl/
Dgxl_pm.c33 uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4); in gxl_pm_set_reset_addr()
41 uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4) + 8; in gxl_pm_reset()
Dgxl_def.h47 #define AML_PSCI_MAILBOX_BASE UL(0xD9013F00) macro