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Searched refs:uint64_t (Results 1 – 25 of 614) sorted by relevance

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/trusted-firmware-a-3.7.0/plat/qti/qtiseclib/inc/
Dqtiseclib_defs.h43 uint64_t x0;
44 uint64_t x1;
45 uint64_t x2;
46 uint64_t x3;
47 uint64_t x4;
48 uint64_t x5;
49 uint64_t x6;
50 uint64_t x7;
51 uint64_t x8;
52 uint64_t x9;
[all …]
/trusted-firmware-a-3.7.0/bl32/tsp/
Dtsp_private.h51 smc_args_t *set_smc_args(uint64_t arg0,
52 uint64_t arg1,
53 uint64_t arg2,
54 uint64_t arg3,
55 uint64_t arg4,
56 uint64_t arg5,
57 uint64_t arg6,
58 uint64_t arg7);
59 smc_args_t *tsp_cpu_resume_main(uint64_t max_off_pwrlvl,
60 uint64_t arg1,
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Dtsp_common.c34 smc_args_t *set_smc_args(uint64_t arg0, in set_smc_args()
35 uint64_t arg1, in set_smc_args()
36 uint64_t arg2, in set_smc_args()
37 uint64_t arg3, in set_smc_args()
38 uint64_t arg4, in set_smc_args()
39 uint64_t arg5, in set_smc_args()
40 uint64_t arg6, in set_smc_args()
41 uint64_t arg7) in set_smc_args()
88 smc_args_t *tsp_system_off_main(uint64_t arg0, in tsp_system_off_main()
89 uint64_t arg1, in tsp_system_off_main()
[all …]
Dtsp_main.c28 uint64_t tsp_main(void) in tsp_main()
55 return (uint64_t) &tsp_vector_table; in tsp_main()
89 smc_args_t *tsp_cpu_off_main(uint64_t arg0, in tsp_cpu_off_main()
90 uint64_t arg1, in tsp_cpu_off_main()
91 uint64_t arg2, in tsp_cpu_off_main()
92 uint64_t arg3, in tsp_cpu_off_main()
93 uint64_t arg4, in tsp_cpu_off_main()
94 uint64_t arg5, in tsp_cpu_off_main()
95 uint64_t arg6, in tsp_cpu_off_main()
96 uint64_t arg7) in tsp_cpu_off_main()
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Dtsp_ffa_main.c82 static int ffa_test_relay(uint64_t arg0, in ffa_test_relay()
83 uint64_t arg1, in ffa_test_relay()
84 uint64_t arg2, in ffa_test_relay()
85 uint64_t arg3, in ffa_test_relay()
86 uint64_t arg4, in ffa_test_relay()
87 uint64_t arg5, in ffa_test_relay()
88 uint64_t arg6, in ffa_test_relay()
89 uint64_t arg7) in ffa_test_relay()
106 static int test_memory_send(ffa_endpoint_id16_t sender, uint64_t handle, in test_memory_send()
209 (uint64_t)ptr, in test_memory_send()
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/trusted-firmware-a-3.7.0/include/services/
Dspmd_svc.h15 uint64_t spmd_ffa_smc_handler(uint32_t smc_fid,
16 uint64_t x1,
17 uint64_t x2,
18 uint64_t x3,
19 uint64_t x4,
22 uint64_t flags);
23 uint64_t spmd_smc_handler(uint32_t smc_fid,
24 uint64_t x1,
25 uint64_t x2,
26 uint64_t x3,
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Dspm_mm_partition.h26 uint64_t mpidr;
33 uint64_t sp_mem_base;
34 uint64_t sp_mem_limit;
35 uint64_t sp_image_base;
36 uint64_t sp_stack_base;
37 uint64_t sp_heap_base;
38 uint64_t sp_ns_comm_buf_base;
39 uint64_t sp_shared_buf_base;
40 uint64_t sp_image_size;
41 uint64_t sp_pcpu_stack_size;
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Del3_spmd_logical_sp.h30 uint64_t func;
31 uint64_t arg1;
32 uint64_t arg2;
33 uint64_t arg3;
34 uint64_t arg4;
35 uint64_t arg5;
36 uint64_t arg6;
37 uint64_t arg7;
38 uint64_t arg8;
39 uint64_t arg9;
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/trusted-firmware-a-3.7.0/plat/nvidia/tegra/soc/t194/drivers/mce/
Dnvg.c29 uint64_t nvg_get_version(void) in nvg_get_version()
31 nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_VERSION); in nvg_get_version()
33 return (uint64_t)nvg_get_result(); in nvg_get_version()
45 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_WAKE_TIME, (uint64_t)wake_time); in nvg_set_wake_time()
64 uint64_t val = 0; in nvg_update_cstate_info()
68 val |= ((uint64_t)cluster & CLUSTER_CSTATE_MASK) | in nvg_update_cstate_info()
74 val |= (((uint64_t)ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT) | in nvg_update_cstate_info()
80 val |= (((uint64_t)system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) | in nvg_update_cstate_info()
90 val |= ((uint64_t)wake_mask & CSTATE_WAKE_MASK_CLEAR) << CSTATE_WAKE_MASK_SHIFT; in nvg_update_cstate_info()
93 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_INFO, val); in nvg_update_cstate_info()
[all …]
/trusted-firmware-a-3.7.0/plat/xilinx/zynqmp/pm_service/
Dzynqmp_pm_svc_main.c110 static uint64_t ttc_fiq_handler(uint32_t id, uint32_t flags, void *handle, in ttc_fiq_handler()
145 static uint64_t __unused __dead2 zynqmp_sgi7_irq(uint32_t id, uint32_t flags, in zynqmp_sgi7_irq()
281 uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, in pm_smc_handler()
282 uint64_t x4, const void *cookie, void *handle, uint64_t flags) in pm_smc_handler()
308 SMC_RET1(handle, (uint64_t)ret); in pm_smc_handler()
313 SMC_RET1(handle, (uint64_t)ret); in pm_smc_handler()
319 uint64_t address = (uint64_t)pm_arg[2] << 32U; in pm_smc_handler()
324 SMC_RET1(handle, (uint64_t)ret); in pm_smc_handler()
329 SMC_RET1(handle, (uint64_t)ret); in pm_smc_handler()
333 SMC_RET1(handle, (uint64_t)ret); in pm_smc_handler()
[all …]
/trusted-firmware-a-3.7.0/plat/rockchip/rk3399/drivers/dp/
Dcdn_dp.c27 static uint64_t *hdcp_key_pdata;
32 uint64_t dp_hdcp_ctrl(uint64_t type) in dp_hdcp_ctrl()
37 hdcp_key_pdata = (uint64_t *)&key; in dp_hdcp_ctrl()
40 if (hdcp_key_pdata == (uint64_t *)(&key + 1)) in dp_hdcp_ctrl()
50 uint64_t dp_hdcp_store_key(uint64_t x1, in dp_hdcp_store_key()
51 uint64_t x2, in dp_hdcp_store_key()
52 uint64_t x3, in dp_hdcp_store_key()
53 uint64_t x4, in dp_hdcp_store_key()
54 uint64_t x5, in dp_hdcp_store_key()
55 uint64_t x6) in dp_hdcp_store_key()
[all …]
Dcdn_dp.h40 uint64_t dp_hdcp_ctrl(uint64_t type);
42 uint64_t dp_hdcp_store_key(uint64_t x1,
43 uint64_t x2,
44 uint64_t x3,
45 uint64_t x4,
46 uint64_t x5,
47 uint64_t x6);
/trusted-firmware-a-3.7.0/services/std_svc/rmmd/
Drmmd_private.h40 uint64_t c_rt_ctx;
45 uint64_t rmmd_rmm_sync_entry(rmmd_rmm_context_t *ctx);
46 __dead2 void rmmd_rmm_sync_exit(uint64_t rc);
49 int rmmd_attest_get_platform_token(uint64_t buf_pa, uint64_t *buf_size,
50 uint64_t c_size);
51 int rmmd_attest_get_signing_key(uint64_t buf_pa, uint64_t *buf_size,
52 uint64_t ecc_curve);
55 uint64_t rmmd_rmm_enter(uint64_t *c_rt_ctx);
56 void __dead2 rmmd_rmm_exit(uint64_t c_rt_ctx, uint64_t ret);
/trusted-firmware-a-3.7.0/services/std_svc/drtm/
Ddrtm_main.h61 uint64_t tpm_features;
62 uint64_t minimum_memory_requirement;
63 uint64_t dma_prot_features;
64 uint64_t boot_pe_id;
65 uint64_t tcb_hash_features;
72 uint64_t dlme_paddr;
73 uint64_t dlme_size;
74 uint64_t dlme_img_off;
75 uint64_t dlme_img_ep_off;
76 uint64_t dlme_img_size;
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/trusted-firmware-a-3.7.0/include/services/trp/
Dtrp_helpers.h28 uint64_t regs[TRP_ARGS_END >> 3];
31 trp_args_t *set_smc_args(uint64_t arg0,
32 uint64_t arg1,
33 uint64_t arg2,
34 uint64_t arg3,
35 uint64_t arg4,
36 uint64_t arg5,
37 uint64_t arg6,
38 uint64_t arg7);
40 __dead2 void trp_boot_abort(uint64_t err);
/trusted-firmware-a-3.7.0/plat/nvidia/tegra/soc/t186/drivers/mce/
Dnvg.c22 uint64_t val = 0ULL; in nvg_enter_cstate()
33 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_WAKE_TIME, wake_time); in nvg_enter_cstate()
37 write_actlr_el1(val | (uint64_t)state); in nvg_enter_cstate()
51 uint64_t val = 0ULL; in nvg_update_cstate_info()
57 val |= ((uint64_t)cluster & CLUSTER_CSTATE_MASK) | in nvg_update_cstate_info()
63 val |= (((uint64_t)ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT) | in nvg_update_cstate_info()
69 val |= (((uint64_t)system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) | in nvg_update_cstate_info()
70 (((uint64_t)sys_state_force << SYSTEM_CSTATE_FORCE_UPDATE_SHIFT) | in nvg_update_cstate_info()
81 val |= ((uint64_t)wake_mask << CSTATE_WAKE_MASK_SHIFT); in nvg_update_cstate_info()
84 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_INFO, val); in nvg_update_cstate_info()
[all …]
/trusted-firmware-a-3.7.0/lib/gpt_rme/
Dgpt_rme_private.h39 #define GPT_BUILD_L1_DESC(_gpi) (((uint64_t)(_gpi) << 4*0) | \
40 ((uint64_t)(_gpi) << 4*1) | \
41 ((uint64_t)(_gpi) << 4*2) | \
42 ((uint64_t)(_gpi) << 4*3) | \
43 ((uint64_t)(_gpi) << 4*4) | \
44 ((uint64_t)(_gpi) << 4*5) | \
45 ((uint64_t)(_gpi) << 4*6) | \
46 ((uint64_t)(_gpi) << 4*7) | \
47 ((uint64_t)(_gpi) << 4*8) | \
48 ((uint64_t)(_gpi) << 4*9) | \
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/trusted-firmware-a-3.7.0/lib/extensions/amu/aarch64/
Damu.c33 uint64_t group0_cnts[AMU_GROUP0_MAX_COUNTERS];
35 uint64_t group1_cnts[AMU_GROUP1_MAX_COUNTERS];
39 uint64_t group0_voffsets[AMU_GROUP0_MAX_COUNTERS - 1U];
41 uint64_t group1_voffsets[AMU_GROUP1_MAX_COUNTERS];
60 static inline __unused uint64_t read_hcr_el2_amvoffen(void) in read_hcr_el2_amvoffen()
66 static inline __unused void write_cptr_el2_tam(uint64_t value) in write_cptr_el2_tam()
72 static inline __unused void ctx_write_scr_el3_amvoffen(cpu_context_t *ctx, uint64_t amvoffen) in ctx_write_scr_el3_amvoffen()
74 uint64_t value = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); in ctx_write_scr_el3_amvoffen()
82 static inline __unused void write_hcr_el2_amvoffen(uint64_t value) in write_hcr_el2_amvoffen()
88 static inline __unused void write_amcr_el0_cg1rz(uint64_t value) in write_amcr_el0_cg1rz()
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/trusted-firmware-a-3.7.0/services/std_svc/spm/el3_spmc/
Dspmc_shared_mem.h26 uint64_t handle;
46 uint64_t next_handle;
56 uint64_t total_length,
58 uint64_t address,
62 uint64_t flags);
66 uint64_t handle_low,
67 uint64_t handle_high,
72 uint64_t flags);
78 uint64_t address,
82 uint64_t flags);
[all …]
/trusted-firmware-a-3.7.0/drivers/arm/gic/v3/
Dgic600ae_fmu_helpers.c50 uint64_t status; in wait_until_fmu_is_idle()
94 uint64_t gic_fmu_read_errfr(uintptr_t base, unsigned int n) in gic_fmu_read_errfr()
100 uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRFR_LO + n * 64U); in gic_fmu_read_errfr()
102 reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_ERRFR_HI + n * 64U) << 32); in gic_fmu_read_errfr()
110 uint64_t gic_fmu_read_errctlr(uintptr_t base, unsigned int n) in gic_fmu_read_errctlr()
116 uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRCTLR_LO + n * 64U); in gic_fmu_read_errctlr()
118 reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_ERRCTLR_HI + n * 64U) << 32); in gic_fmu_read_errctlr()
126 uint64_t gic_fmu_read_errstatus(uintptr_t base, unsigned int n) in gic_fmu_read_errstatus()
132 uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRSTATUS_LO + n * 64U); in gic_fmu_read_errstatus()
134 reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_ERRSTATUS_HI + n * 64U) << 32); in gic_fmu_read_errstatus()
[all …]
/trusted-firmware-a-3.7.0/lib/extensions/amu/
Damu_private.h23 uint64_t amu_group0_cnt_read_internal(unsigned int idx);
24 void amu_group0_cnt_write_internal(unsigned int idx, uint64_t val);
26 uint64_t amu_group1_cnt_read_internal(unsigned int idx);
27 void amu_group1_cnt_write_internal(unsigned int idx, uint64_t val);
31 uint64_t amu_group0_voffset_read_internal(unsigned int idx);
32 void amu_group0_voffset_write_internal(unsigned int idx, uint64_t val);
34 uint64_t amu_group1_voffset_read_internal(unsigned int idx);
35 void amu_group1_voffset_write_internal(unsigned int idx, uint64_t val);
/trusted-firmware-a-3.7.0/plat/mediatek/common/
Dmtk_plat_common.h38 void bl31_prepare_kernel_entry(uint64_t k32_64);
40 void boot_to_kernel(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4);
41 uint64_t get_kernel_info_pc(void);
42 uint64_t get_kernel_info_r0(void);
43 uint64_t get_kernel_info_r1(void);
44 uint64_t get_kernel_info_r2(void);
/trusted-firmware-a-3.7.0/plat/xilinx/common/pm_service/
Dpm_svc_main.c51 static uint64_t ipi_fiq_handler(uint32_t id, uint32_t flags, void *handle, in ipi_fiq_handler()
191 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U); in eemi_for_compatibility()
201 SMC_RET2(handle, (uint64_t)ret | ((uint64_t)data[0] << 32U), in eemi_for_compatibility()
202 (uint64_t)data[1] | ((uint64_t)data[2] << 32U)); in eemi_for_compatibility()
210 SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32U), in eemi_for_compatibility()
211 (uint64_t)result[1] | ((uint64_t)result[2] << 32U)); in eemi_for_compatibility()
218 SMC_RET1(handle, (uint64_t)ret); in eemi_for_compatibility()
319 (uint64_t)result[0] | ((uint64_t)result[1] << 32U), in TF_A_specific_handler()
320 (uint64_t)result[2] | ((uint64_t)result[3] << 32U)); in TF_A_specific_handler()
324 SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS | in TF_A_specific_handler()
[all …]
/trusted-firmware-a-3.7.0/plat/arm/common/aarch64/
Darm_pauth.c19 uint64_t return_addr = (uint64_t)__builtin_return_address(0U); in plat_init_apkey()
20 uint64_t frame_addr = (uint64_t)__builtin_frame_address(0U); in plat_init_apkey()
21 uint64_t cntpct = read_cntpct_el0(); in plat_init_apkey()
24 uint64_t key_lo = (return_addr << 13) ^ frame_addr ^ cntpct; in plat_init_apkey()
25 uint64_t key_hi = (frame_addr << 15) ^ return_addr ^ cntpct; in plat_init_apkey()
/trusted-firmware-a-3.7.0/services/std_svc/rmmd/trp/
Dtrp_private.h45 uint64_t trp_smc(trp_args_t *);
51 void trp_setup(uint64_t x0,
52 uint64_t x1,
53 uint64_t x2,
54 uint64_t x3);
57 int trp_validate_warmboot_args(uint64_t x0, uint64_t x1,
58 uint64_t x2, uint64_t x3);

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