| /trusted-firmware-a-3.7.0/drivers/arm/fvp/ |
| D | fvp_pwrc.c | 27 static unsigned int fvp_pwrc_core_id(u_register_t mpidr) in fvp_pwrc_core_id() argument
29 return (unsigned int)(mpidr & FVP_PWRC_ID_MASK); in fvp_pwrc_core_id()
32 unsigned int fvp_pwrc_get_cpu_wkr(u_register_t mpidr) in fvp_pwrc_get_cpu_wkr() argument
34 unsigned int id = fvp_pwrc_core_id(mpidr); in fvp_pwrc_get_cpu_wkr()
39 unsigned int fvp_pwrc_read_psysr(u_register_t mpidr) in fvp_pwrc_read_psysr() argument
42 unsigned int id = fvp_pwrc_core_id(mpidr); in fvp_pwrc_read_psysr()
51 void fvp_pwrc_write_pponr(u_register_t mpidr) in fvp_pwrc_write_pponr() argument
53 unsigned int id = fvp_pwrc_core_id(mpidr); in fvp_pwrc_write_pponr()
60 void fvp_pwrc_write_ppoffr(u_register_t mpidr) in fvp_pwrc_write_ppoffr() argument
62 unsigned int id = fvp_pwrc_core_id(mpidr); in fvp_pwrc_write_ppoffr()
[all …]
|
| /trusted-firmware-a-3.7.0/plat/mediatek/mt8173/ |
| D | power_tracer.c | 14 void trace_power_flow(unsigned long mpidr, unsigned char mode) in trace_power_flow() argument
19 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
20 (mpidr & MPIDR_CPU_MASK)); in trace_power_flow()
24 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
25 (mpidr & MPIDR_CPU_MASK)); in trace_power_flow()
29 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
30 (mpidr & MPIDR_CPU_MASK)); in trace_power_flow()
34 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
38 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
42 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
|
| D | plat_pm.c | 105 static struct cluster_context *get_cluster_data(unsigned long mpidr) in get_cluster_data() argument
109 clusterid = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in get_cluster_data()
114 static struct core_context *get_core_data(unsigned long mpidr) in get_core_data() argument
119 cluster = get_cluster_data(mpidr); in get_core_data()
120 cpuid = mpidr & MPIDR_CPU_MASK; in get_core_data()
207 static void mt_cpu_save(unsigned long mpidr) in mt_cpu_save() argument
211 core = get_core_data(mpidr); in mt_cpu_save()
218 static void mt_cpu_restore(unsigned long mpidr) in mt_cpu_restore() argument
222 core = get_core_data(mpidr); in mt_cpu_restore()
226 static void mt_platform_save_context(unsigned long mpidr) in mt_platform_save_context() argument
[all …]
|
| /trusted-firmware-a-3.7.0/plat/arm/common/ |
| D | arm_topology.c | 17 int arm_check_mpidr(u_register_t mpidr) in arm_check_mpidr() argument
29 cluster_id = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK; in arm_check_mpidr()
30 cpu_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in arm_check_mpidr()
31 pe_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in arm_check_mpidr()
34 cluster_id = (unsigned int) ((mpidr >> MPIDR_AFF1_SHIFT) & in arm_check_mpidr()
36 cpu_id = (unsigned int) ((mpidr >> MPIDR_AFF0_SHIFT) & in arm_check_mpidr()
40 mpidr &= MPIDR_AFFINITY_MASK; in arm_check_mpidr()
41 if ((mpidr & valid_mask) != 0U) in arm_check_mpidr()
49 if (cpu_id >= plat_arm_get_cluster_core_count(mpidr)) in arm_check_mpidr()
53 if (pe_id >= plat_arm_get_cpu_pe_count(mpidr)) in arm_check_mpidr()
|
| /trusted-firmware-a-3.7.0/plat/amlogic/g12a/ |
| D | g12a_pm.c | 30 static void g12a_pm_set_reset_addr(u_register_t mpidr, uint64_t value) in g12a_pm_set_reset_addr() argument
32 unsigned int core = plat_calc_core_pos(mpidr); in g12a_pm_set_reset_addr()
38 static void g12a_pm_reset(u_register_t mpidr) in g12a_pm_reset() argument
40 unsigned int core = plat_calc_core_pos(mpidr); in g12a_pm_reset()
50 u_register_t mpidr = read_mpidr_el1(); in g12a_system_reset() local
69 g12a_pm_reset(mpidr); in g12a_system_reset()
81 u_register_t mpidr = read_mpidr_el1(); in g12a_system_off() local
91 g12a_pm_set_reset_addr(mpidr, 0); in g12a_system_off()
92 g12a_pm_reset(mpidr); in g12a_system_off()
100 static int32_t g12a_pwr_domain_on(u_register_t mpidr) in g12a_pwr_domain_on() argument
[all …]
|
| /trusted-firmware-a-3.7.0/plat/amlogic/gxl/ |
| D | gxl_pm.c | 30 static void gxl_pm_set_reset_addr(u_register_t mpidr, uint64_t value) in gxl_pm_set_reset_addr() argument
32 unsigned int core = plat_calc_core_pos(mpidr); in gxl_pm_set_reset_addr()
38 static void gxl_pm_reset(u_register_t mpidr) in gxl_pm_reset() argument
40 unsigned int core = plat_calc_core_pos(mpidr); in gxl_pm_reset()
50 u_register_t mpidr = read_mpidr_el1(); in gxl_system_reset() local
69 gxl_pm_reset(mpidr); in gxl_system_reset()
81 u_register_t mpidr = read_mpidr_el1(); in gxl_system_off() local
91 gxl_pm_set_reset_addr(mpidr, 0); in gxl_system_off()
92 gxl_pm_reset(mpidr); in gxl_system_off()
100 static int32_t gxl_pwr_domain_on(u_register_t mpidr) in gxl_pwr_domain_on() argument
[all …]
|
| /trusted-firmware-a-3.7.0/plat/marvell/armada/common/ |
| D | marvell_topology.c | 44 int marvell_check_mpidr(u_register_t mpidr) in marvell_check_mpidr() argument
48 mpidr &= MPIDR_AFFINITY_MASK; in marvell_check_mpidr()
50 if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK | in marvell_check_mpidr()
55 nb_id = MPIDR_AFFLVL3_VAL(mpidr); in marvell_check_mpidr()
56 cluster_id = MPIDR_AFFLVL1_VAL(mpidr); in marvell_check_mpidr()
57 cpu_id = MPIDR_AFFLVL0_VAL(mpidr); in marvell_check_mpidr()
78 int plat_core_pos_by_mpidr(u_register_t mpidr) in plat_core_pos_by_mpidr() argument
80 if (marvell_check_mpidr(mpidr) == -1) in plat_core_pos_by_mpidr()
83 return plat_marvell_calc_core_pos(mpidr); in plat_core_pos_by_mpidr()
|
| /trusted-firmware-a-3.7.0/plat/hisilicon/hikey/ |
| D | hikey_pm.c | 32 static int hikey_pwr_domain_on(u_register_t mpidr) in hikey_pwr_domain_on() argument
37 cluster = MPIDR_AFFLVL1_VAL(mpidr); in hikey_pwr_domain_on()
38 cpu = MPIDR_AFFLVL0_VAL(mpidr); in hikey_pwr_domain_on()
52 unsigned long mpidr; in hikey_pwr_domain_on_finish() local
55 mpidr = read_mpidr(); in hikey_pwr_domain_on_finish()
56 cluster = MPIDR_AFFLVL1_VAL(mpidr); in hikey_pwr_domain_on_finish()
57 cpu = MPIDR_AFFLVL0_VAL(mpidr); in hikey_pwr_domain_on_finish()
65 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); in hikey_pwr_domain_on_finish()
78 unsigned long mpidr; in hikey_pwr_domain_off() local
81 mpidr = read_mpidr(); in hikey_pwr_domain_off()
[all …]
|
| /trusted-firmware-a-3.7.0/plat/amlogic/axg/ |
| D | axg_pm.c | 29 static void axg_pm_set_reset_addr(u_register_t mpidr, uint64_t value) in axg_pm_set_reset_addr() argument
31 unsigned int core = plat_calc_core_pos(mpidr); in axg_pm_set_reset_addr()
37 static void axg_pm_reset(u_register_t mpidr, uint32_t value) in axg_pm_reset() argument
39 unsigned int core = plat_calc_core_pos(mpidr); in axg_pm_reset()
47 u_register_t mpidr = read_mpidr_el1(); in axg_system_reset() local
58 axg_pm_reset(mpidr, 0); in axg_system_reset()
68 u_register_t mpidr = read_mpidr_el1(); in axg_system_off() local
79 axg_pm_set_reset_addr(mpidr, 0); in axg_system_off()
80 axg_pm_reset(mpidr, 0); in axg_system_off()
89 static int32_t axg_pwr_domain_on(u_register_t mpidr) in axg_pwr_domain_on() argument
[all …]
|
| /trusted-firmware-a-3.7.0/plat/arm/board/arm_fpga/ |
| D | fpga_topology.c | 54 int plat_core_pos_by_mpidr(u_register_t mpidr) in plat_core_pos_by_mpidr() argument
58 mpidr &= (MPID_MASK & ~(MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT)); in plat_core_pos_by_mpidr()
59 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); in plat_core_pos_by_mpidr()
61 if ((MPIDR_AFFLVL2_VAL(mpidr) >= FPGA_MAX_CLUSTER_COUNT) || in plat_core_pos_by_mpidr()
62 (MPIDR_AFFLVL1_VAL(mpidr) >= FPGA_MAX_CPUS_PER_CLUSTER) || in plat_core_pos_by_mpidr()
63 (MPIDR_AFFLVL0_VAL(mpidr) >= FPGA_MAX_PE_PER_CPU)) { in plat_core_pos_by_mpidr()
64 ERROR ("Invalid mpidr: 0x%08x\n", (uint32_t)mpidr); in plat_core_pos_by_mpidr()
69 core_pos = plat_fpga_calc_core_pos(mpidr); in plat_core_pos_by_mpidr()
|
| /trusted-firmware-a-3.7.0/plat/mediatek/mt8186/ |
| D | plat_topology.c | 36 int plat_core_pos_by_mpidr(u_register_t mpidr) in plat_core_pos_by_mpidr() argument
42 if ((mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) != 0) { in plat_core_pos_by_mpidr()
45 return plat_mediatek_calc_core_pos(mpidr); in plat_core_pos_by_mpidr()
48 mpidr &= MPIDR_AFFINITY_MASK; in plat_core_pos_by_mpidr()
50 if ((mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) != 0) { in plat_core_pos_by_mpidr()
54 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
55 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
| /trusted-firmware-a-3.7.0/plat/mediatek/mt8192/ |
| D | plat_topology.c | 41 int plat_core_pos_by_mpidr(u_register_t mpidr) in plat_core_pos_by_mpidr() argument
47 if (mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) { in plat_core_pos_by_mpidr()
50 return plat_mediatek_calc_core_pos(mpidr); in plat_core_pos_by_mpidr()
53 mpidr &= MPIDR_AFFINITY_MASK; in plat_core_pos_by_mpidr()
55 if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) { in plat_core_pos_by_mpidr()
59 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
60 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
| /trusted-firmware-a-3.7.0/plat/mediatek/mt8195/ |
| D | plat_topology.c | 36 int plat_core_pos_by_mpidr(u_register_t mpidr) in plat_core_pos_by_mpidr() argument
42 if ((mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) != 0) { in plat_core_pos_by_mpidr()
45 return plat_mediatek_calc_core_pos(mpidr); in plat_core_pos_by_mpidr()
48 mpidr &= MPIDR_AFFINITY_MASK; in plat_core_pos_by_mpidr()
50 if ((mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) != 0) { in plat_core_pos_by_mpidr()
54 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
55 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
| /trusted-firmware-a-3.7.0/plat/arm/board/fvp/ |
| D | fvp_topology.c | 76 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr) in plat_arm_get_cluster_core_count() argument
87 int plat_core_pos_by_mpidr(u_register_t mpidr) in plat_core_pos_by_mpidr() argument
93 thread_id = MPIDR_AFFLVL0_VAL(mpidr); in plat_core_pos_by_mpidr()
94 cpu_id = MPIDR_AFFLVL1_VAL(mpidr); in plat_core_pos_by_mpidr()
95 clus_id = MPIDR_AFFLVL2_VAL(mpidr); in plat_core_pos_by_mpidr()
98 cpu_id = MPIDR_AFFLVL0_VAL(mpidr); in plat_core_pos_by_mpidr()
99 clus_id = MPIDR_AFFLVL1_VAL(mpidr); in plat_core_pos_by_mpidr()
109 if (fvp_pwrc_read_psysr(mpidr) == PSYSR_INVALID) in plat_core_pos_by_mpidr()
121 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); in plat_core_pos_by_mpidr()
122 return (int) plat_arm_calc_core_pos(mpidr); in plat_core_pos_by_mpidr()
|
| /trusted-firmware-a-3.7.0/plat/rpi/common/ |
| D | rpi3_topology.c | 37 int plat_core_pos_by_mpidr(u_register_t mpidr) in plat_core_pos_by_mpidr() argument
41 mpidr &= MPIDR_AFFINITY_MASK; in plat_core_pos_by_mpidr()
42 if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) { in plat_core_pos_by_mpidr()
46 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
47 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
57 return plat_rpi3_calc_core_pos(mpidr); in plat_core_pos_by_mpidr()
|
| /trusted-firmware-a-3.7.0/plat/amlogic/common/ |
| D | aml_topology.c | 35 int plat_core_pos_by_mpidr(u_register_t mpidr) in plat_core_pos_by_mpidr() argument
39 mpidr &= MPIDR_AFFINITY_MASK; in plat_core_pos_by_mpidr()
40 if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) in plat_core_pos_by_mpidr()
43 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
44 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
52 return plat_calc_core_pos(mpidr); in plat_core_pos_by_mpidr()
|
| /trusted-firmware-a-3.7.0/plat/qemu/common/ |
| D | topology.c | 39 int plat_core_pos_by_mpidr(u_register_t mpidr) in plat_core_pos_by_mpidr() argument
43 mpidr &= MPIDR_AFFINITY_MASK; in plat_core_pos_by_mpidr()
44 if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) in plat_core_pos_by_mpidr()
47 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
48 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
56 return plat_qemu_calc_core_pos(mpidr); in plat_core_pos_by_mpidr()
|
| /trusted-firmware-a-3.7.0/drivers/renesas/common/pwrc/ |
| D | pwrc.h | 44 void rcar_pwrc_disable_interrupt_wakeup(u_register_t mpidr);
45 void rcar_pwrc_enable_interrupt_wakeup(u_register_t mpidr);
47 void rcar_pwrc_clusteroff(u_register_t mpidr);
48 void rcar_pwrc_cpuoff(u_register_t mpidr);
49 void rcar_pwrc_cpuon(u_register_t mpidr);
50 int32_t rcar_pwrc_cpu_on_check(u_register_t mpidr);
53 uint32_t rcar_pwrc_get_cpu_wkr(u_register_t mpidr);
54 uint32_t rcar_pwrc_status(u_register_t mpidr);
56 uint32_t rcar_pwrc_get_mpidr_cluster(u_register_t mpidr);
|
| /trusted-firmware-a-3.7.0/plat/renesas/common/ |
| D | plat_pm.c | 45 static void rcar_program_mailbox(u_register_t mpidr, uintptr_t address) in rcar_program_mailbox() argument
48 uint64_t linear_id = plat_core_pos_by_mpidr(mpidr); in rcar_program_mailbox()
67 static int rcar_pwr_domain_on(u_register_t mpidr) in rcar_pwr_domain_on() argument
69 rcar_program_mailbox(mpidr, rcar_sec_entrypoint); in rcar_pwr_domain_on()
70 rcar_pwrc_cpuon(mpidr); in rcar_pwr_domain_on()
78 u_register_t mpidr = read_mpidr_el1(); in rcar_pwr_domain_on_finish() local
84 rcar_program_mailbox(mpidr, 0); in rcar_pwr_domain_on_finish()
85 rcar_pwrc_enable_interrupt_wakeup(mpidr); in rcar_pwr_domain_on_finish()
96 u_register_t mpidr = read_mpidr_el1(); in rcar_pwr_domain_off() local
98 rcar_pwrc_disable_interrupt_wakeup(mpidr); in rcar_pwr_domain_off()
[all …]
|
| /trusted-firmware-a-3.7.0/plat/arm/css/common/ |
| D | css_topology.c | 22 int plat_core_pos_by_mpidr(u_register_t mpidr) in plat_core_pos_by_mpidr() argument
24 if (arm_check_mpidr(mpidr) == 0) { in plat_core_pos_by_mpidr()
32 mpidr |= MPIDR_MT_MASK; in plat_core_pos_by_mpidr()
34 return plat_arm_calc_core_pos(mpidr); in plat_core_pos_by_mpidr()
44 unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr) in plat_arm_get_cpu_pe_count() argument
|
| /trusted-firmware-a-3.7.0/plat/qemu/qemu_sbsa/ |
| D | sbsa_topology.c | 39 int plat_core_pos_by_mpidr(u_register_t mpidr) in plat_core_pos_by_mpidr() argument
43 mpidr &= MPIDR_AFFINITY_MASK; in plat_core_pos_by_mpidr()
44 if ((mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) != 0U) { in plat_core_pos_by_mpidr()
49 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
50 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
62 return plat_qemu_calc_core_pos(mpidr); in plat_core_pos_by_mpidr()
|
| /trusted-firmware-a-3.7.0/include/drivers/arm/fvp/ |
| D | fvp_pwrc.h | 45 void fvp_pwrc_write_pcoffr(u_register_t mpidr);
46 void fvp_pwrc_write_ppoffr(u_register_t mpidr);
47 void fvp_pwrc_write_pponr(u_register_t mpidr);
48 void fvp_pwrc_set_wen(u_register_t mpidr);
49 void fvp_pwrc_clr_wen(u_register_t mpidr);
50 unsigned int fvp_pwrc_read_psysr(u_register_t mpidr);
51 unsigned int fvp_pwrc_get_cpu_wkr(u_register_t mpidr);
|
| /trusted-firmware-a-3.7.0/plat/allwinner/common/ |
| D | sunxi_topology.c | 21 int plat_core_pos_by_mpidr(u_register_t mpidr) in plat_core_pos_by_mpidr() argument
23 unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr); in plat_core_pos_by_mpidr()
24 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); in plat_core_pos_by_mpidr()
26 if (MPIDR_AFFLVL3_VAL(mpidr) > 0 || in plat_core_pos_by_mpidr()
27 MPIDR_AFFLVL2_VAL(mpidr) > 0 || in plat_core_pos_by_mpidr()
|
| /trusted-firmware-a-3.7.0/plat/intel/soc/common/ |
| D | socfpga_topology.c | 27 int plat_core_pos_by_mpidr(u_register_t mpidr) in plat_core_pos_by_mpidr() argument
31 mpidr &= MPIDR_AFFINITY_MASK; in plat_core_pos_by_mpidr()
33 if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) in plat_core_pos_by_mpidr()
36 cluster_id = (mpidr >> PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
37 cpu_id = (mpidr >> PLAT_CPU_ID_MPIDR_AFF_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
| /trusted-firmware-a-3.7.0/plat/nuvoton/common/ |
| D | nuvoton_topology.c | 32 int plat_core_pos_by_mpidr(u_register_t mpidr) in plat_core_pos_by_mpidr() argument
36 mpidr &= MPIDR_AFFINITY_MASK; in plat_core_pos_by_mpidr()
38 if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) { in plat_core_pos_by_mpidr()
42 cluster_id = (unsigned int)MPIDR_AFFLVL1_VAL(mpidr); in plat_core_pos_by_mpidr()
43 cpu_id = (unsigned int)MPIDR_AFFLVL0_VAL(mpidr); in plat_core_pos_by_mpidr()
|
