Searched refs:cwl (Results 1 – 4 of 4) sorted by relevance
233 pdram_timing->cwl = 6; in ddr3_get_parameter()236 pdram_timing->cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0xf; in ddr3_get_parameter()268 pdram_timing->mr[2] = DDR3_MR2_CWL(pdram_timing->cwl); in ddr3_get_parameter()348 pdram_timing->todton = pdram_timing->cwl - 2; in ddr3_get_parameter()438 pdram_timing->cwl = 2; in lpddr2_get_parameter()442 pdram_timing->cwl = 2; in lpddr2_get_parameter()446 pdram_timing->cwl = 3; in lpddr2_get_parameter()450 pdram_timing->cwl = 4; in lpddr2_get_parameter()454 pdram_timing->cwl = 4; in lpddr2_get_parameter()680 pdram_timing->cwl = 3; in lpddr3_get_parameter()[all …]
224 uint32_t cwl; member285 static uint32_t get_wrlat_adj(uint32_t dram_type, uint32_t cwl) in get_wrlat_adj() argument303 if (cwl == p[i].cwl) in get_wrlat_adj()532 (pdram_timing->cwl << 24)); in gen_rk3399_ctl_params_f0()654 (get_wrlat_adj(timing_config->dram_type, pdram_timing->cwl) in gen_rk3399_ctl_params_f0()684 tmp = pdram_timing->cl - pdram_timing->cwl; in gen_rk3399_ctl_params_f0()784 (pdram_timing->cwl << 16)); in gen_rk3399_ctl_params_f1()903 pdram_timing->cwl) << 8) | in gen_rk3399_ctl_params_f1()934 tmp = pdram_timing->cl - pdram_timing->cwl; in gen_rk3399_ctl_params_f1()1100 tmp = pdram_timing->cl - pdram_timing->cwl; in gen_rk3399_pi_params_f0()[all …]
169 uint32_t cwl; member
572 unsigned int cwl = cal_cwl(clk); in cal_ddr_sdram_mode() local637 switch (cwl) { in cal_ddr_sdram_mode()642 cwl -= 9; in cal_ddr_sdram_mode()645 cwl -= 10; in cal_ddr_sdram_mode()648 cwl -= 11; in cal_ddr_sdram_mode()651 cwl -= 12; in cal_ddr_sdram_mode()654 cwl -= 13; in cal_ddr_sdram_mode()670 ((cwl & 0x7) << 3); in cal_ddr_sdram_mode()
