| /trusted-firmware-a-3.7.0/plat/mediatek/drivers/cpu_pm/cpcv3_2/ |
| D | mt_cpu_pm.h | 40 #define PER_CPU_PWR_DATA(ctrl, cluster, core) \ argument
42 ctrl.rvbaraddr_l = CORE_RVBRADDR_##cluster##_##core##_L; \
43 ctrl.arch_addr = MCUCFG_MP0_CLUSTER_CFG5; \
44 ctrl.pwpr = SPM_MP##cluster##_CPU##core##_PWR_CON; \
47 #define PER_CPU_PWR_CTRL(ctrl, cpu) ({ \ argument
50 PER_CPU_PWR_DATA(ctrl, 0, 0); \
53 PER_CPU_PWR_DATA(ctrl, 0, 1); \
56 PER_CPU_PWR_DATA(ctrl, 0, 2); \
59 PER_CPU_PWR_DATA(ctrl, 0, 3); \
62 PER_CPU_PWR_DATA(ctrl, 0, 4); \
[all …]
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| /trusted-firmware-a-3.7.0/drivers/brcm/emmc/ |
| D | emmc_chal_sd.c | 87 mmio_clrsetbits_32(handle->ctrl.sdRegBaseAddr + in chal_sd_set_power()
101 rc = mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_set_power()
119 mmio_setbits_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL_OFFSET, in chal_sd_set_power()
123 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_ARG_OFFSET, 0); in chal_sd_set_power()
124 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CMD_OFFSET, 0); in chal_sd_set_power()
132 rc = mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_set_power()
164 mmio_clrsetbits_32(handle->ctrl.sdRegBaseAddr + in chal_sd_set_dma_boundary()
175 handle->ctrl.sdRegBaseAddr = sdBase; in chal_sd_setup_handler()
176 handle->ctrl.hostRegBaseAddr = hostBase; in chal_sd_setup_handler()
177 handle->ctrl.present = 0; in chal_sd_setup_handler()
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| D | emmc_csl_sdcard.c | 196 handle->device->ctrl.argReg = 0; in abort_err()
197 handle->device->ctrl.cmdIndex = SD_CMD_STOP_TRANSMISSION; in abort_err()
205 handle->device->ctrl.cmdIndex, in abort_err()
206 handle->device->ctrl.argReg, options); in abort_err()
223 process_cmd_response(handle, handle->device->ctrl.cmdIndex, in abort_err()
270 if (handle->device->ctrl.cmdStatus == SD_OK) in process_data_xfer()
273 check_error(handle, handle->device->ctrl.cmdStatus); in process_data_xfer()
299 if (handle->device->ctrl.cmdStatus == SD_OK) in process_data_xfer()
302 check_error(handle, handle->device->ctrl.cmdStatus); in process_data_xfer()
338 handle->device->ctrl.present = 0; /* init card present to be no card */ in init_card()
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| D | emmc_csl_sdcmd.c | 76 handle->device->ctrl.rca = 0x5; in sd_cmd3()
77 argument = handle->device->ctrl.rca << SD_CMD7_ARG_RCA_SHIFT; in sd_cmd3()
87 handle->device->ctrl.rca = 0; in sd_cmd3()
157 argument = handle->device->ctrl.rca << SD_CMD7_ARG_RCA_SHIFT; in sd_cmd9()
250 argument = handle->device->ctrl.rca << SD_CMD7_ARG_RCA_SHIFT; in sd_cmd13()
284 handle->device->ctrl.rca, res, resp.cardStatus); in sd_cmd16()
325 handle->device->ctrl.rca, res, resp.cardStatus); in sd_cmd17()
379 handle->device->ctrl.rca, res, resp.cardStatus); in sd_cmd18()
433 handle->device->ctrl.rca, res); in card_sts_resp()
550 handle->device->ctrl.rca, res, &resp.cardStatus); in sd_cmd24()
[all …]
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| D | emmc_pboot_hal_memory_drv.c | 341 if ((p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY) == 0) { in sdio_read()
348 if (p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY) { in sdio_read()
391 if (p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY) { in sdio_read()
418 if (p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY) { in sdio_read()
472 if ((p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY) == 0) { in sdio_write()
479 if (p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY) { in sdio_write()
541 if (p_sdhandle->device->ctrl.ocr & in sdio_write()
566 if (p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY) in sdio_write()
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| /trusted-firmware-a-3.7.0/drivers/marvell/ |
| D | amb_adec.c | 77 uint32_t ctrl, base, size; in amb_enable_win() local
85 ctrl = (size << AMB_SIZE_OFFSET) | (win->target_id << AMB_ATTR_OFFSET); in amb_enable_win()
89 mmio_write_32(AMB_WIN_CR_OFFSET(win_num), ctrl); in amb_enable_win()
92 ctrl |= WIN_ENABLE_BIT; in amb_enable_win()
93 mmio_write_32(AMB_WIN_CR_OFFSET(win_num), ctrl); in amb_enable_win()
99 uint32_t ctrl, base, win_id, attr; in dump_amb_adec() local
106 ctrl = mmio_read_32(AMB_WIN_CR_OFFSET(win_id)); in dump_amb_adec()
107 if (ctrl & WIN_ENABLE_BIT) { in dump_amb_adec()
109 attr = (ctrl >> AMB_ATTR_OFFSET) & AMB_ATTR_MASK; in dump_amb_adec()
110 size_count = (ctrl >> AMB_SIZE_OFFSET) & AMB_SIZE_MASK; in dump_amb_adec()
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| /trusted-firmware-a-3.7.0/plat/marvell/armada/a3k/common/ |
| D | io_addr_dec.c | 40 uint32_t ctrl = 0; in set_io_addr_dec_win() local
44 ctrl = ((win_size / MVEBU_WIN_BASE_SIZE_ALIGNMENT) - 1) << in set_io_addr_dec_win()
47 ctrl |= dec_win->win_attr << MVEBU_DEC_WIN_CTRL_ATTR_OFF; in set_io_addr_dec_win()
49 ctrl |= DRAM_CPU_DEC_TARGET_NUM << MVEBU_DEC_WIN_CTRL_TARGET_OFF; in set_io_addr_dec_win()
64 win_id, dec_win->win_offset), ctrl); in set_io_addr_dec_win()
66 ctrl |= MVEBU_DEC_WIN_ENABLE << MVEBU_DEC_WIN_CTRL_EN_OFF; in set_io_addr_dec_win()
68 win_id, dec_win->win_offset), ctrl); in set_io_addr_dec_win()
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| /trusted-firmware-a-3.7.0/drivers/rpi3/rng/ |
| D | rpi3_rng.c | 19 uint32_t int_mask, ctrl; in rpi3_rng_initialize() local
22 ctrl = mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_CTRL_OFFSET); in rpi3_rng_initialize()
23 if ((ctrl & RPI3_RNG_CTRL_ENABLE) != 0U) { in rpi3_rng_initialize()
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| /trusted-firmware-a-3.7.0/plat/brcm/board/stingray/src/ |
| D | paxb.c | 380 uintptr_t ctrl = (uintptr_t)(PCIE_CORE_SOFT_RST_CFG_BASE + offset); in pcie_core_soft_reset() local
383 mmio_clrbits_32(ctrl, PCIE_CORE_SOFT_RST); in pcie_core_soft_reset()
388 mmio_setbits_32(ctrl, PCIE_CORE_SOFT_RST); in pcie_core_soft_reset()
391 static int pcie_core_pwron_switch(uintptr_t ctrl, uintptr_t status, in pcie_core_pwron_switch() argument
398 mmio_setbits_32(ctrl, mask); in pcie_core_pwron_switch()
411 static int pcie_core_pwr_seq(uintptr_t ctrl, uintptr_t status) in pcie_core_pwr_seq() argument
422 ret = pcie_core_pwron_switch(ctrl, status, PCIE_CORE_PWR_ARR_POWERON); in pcie_core_pwr_seq()
426 ret = pcie_core_pwron_switch(ctrl, status, PCIE_CORE_PWR_ARR_POWEROK); in pcie_core_pwr_seq()
430 ret = pcie_core_pwron_switch(ctrl, status, PCIE_CORE_PWR_POWERON); in pcie_core_pwr_seq()
434 ret = pcie_core_pwron_switch(ctrl, status, PCIE_CORE_PWR_POWEROK); in pcie_core_pwr_seq()
[all …]
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| /trusted-firmware-a-3.7.0/plat/imx/common/include/sci/svc/pad/ |
| D | sci_pad_api.h | 257 sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t ctrl);
277 sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t *ctrl);
339 sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl,
366 uint32_t *ctrl, sc_pad_wakeup_t *wakeup);
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| /trusted-firmware-a-3.7.0/plat/imx/common/sci/svc/pad/ |
| D | pad_rpc_clnt.c | 83 sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t ctrl) in sc_pad_set_gp() argument
91 RPC_U32(&msg, 0U) = (uint32_t)ctrl; in sc_pad_set_gp()
101 sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t *ctrl) in sc_pad_get_gp() argument
114 if (ctrl != NULL) { in sc_pad_get_gp()
115 *ctrl = RPC_U32(&msg, 0U); in sc_pad_get_gp()
162 sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl, in sc_pad_set_all() argument
171 RPC_U32(&msg, 0U) = (uint32_t)ctrl; in sc_pad_set_all()
187 uint32_t *ctrl, sc_pad_wakeup_t *wakeup) in sc_pad_get_all() argument
200 if (ctrl != NULL) { in sc_pad_get_all()
201 *ctrl = RPC_U32(&msg, 0U); in sc_pad_get_all()
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| /trusted-firmware-a-3.7.0/plat/imx/common/include/sci/svc/misc/ |
| D | sci_misc_api.h | 121 sc_ctrl_t ctrl, uint32_t val);
141 sc_ctrl_t ctrl, uint32_t *val);
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| /trusted-firmware-a-3.7.0/plat/mediatek/drivers/apusys/mt8188/ |
| D | apusys_power.c | 50 static void apu_backup_restore(enum APU_BACKUP_RESTORE_CTRL ctrl) in apu_backup_restore() argument
70 switch (ctrl) { in apu_backup_restore()
82 ERROR(MODULE_TAG "%s invalid op: %d\n", __func__, ctrl); in apu_backup_restore()
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| /trusted-firmware-a-3.7.0/plat/imx/common/sci/svc/misc/ |
| D | misc_rpc_clnt.c | 32 sc_ctrl_t ctrl, uint32_t val) in sc_misc_set_control() argument
40 RPC_U32(&msg, 0U) = (uint32_t)ctrl; in sc_misc_set_control()
52 sc_ctrl_t ctrl, uint32_t *val) in sc_misc_get_control() argument
60 RPC_U32(&msg, 0U) = (uint32_t)ctrl; in sc_misc_get_control()
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| /trusted-firmware-a-3.7.0/include/drivers/brcm/emmc/ |
| D | emmc_chal_sd.h | 166 struct sd_ctrl_info ctrl; /* SD info */ member
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