| /trusted-firmware-a-3.7.0/plat/brcm/common/ |
| D | brcm_bl31_setup.c | 30 static entry_point_info_t bl33_image_ep_info; variable
65 ? &bl33_image_ep_info : &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
113 SET_PARAM_HEAD(&bl33_image_ep_info, in brcm_bl31_early_platform_setup()
121 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); in brcm_bl31_early_platform_setup()
123 bl33_image_ep_info.spsr = brcm_get_spsr_for_bl33_entry(); in brcm_bl31_early_platform_setup()
124 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in brcm_bl31_early_platform_setup()
133 bl33_image_ep_info.args.arg0 = (u_register_t)PRELOADED_DTB_BASE; in brcm_bl31_early_platform_setup()
134 bl33_image_ep_info.args.arg1 = 0U; in brcm_bl31_early_platform_setup()
135 bl33_image_ep_info.args.arg2 = 0U; in brcm_bl31_early_platform_setup()
136 bl33_image_ep_info.args.arg3 = 0U; in brcm_bl31_early_platform_setup()
[all …]
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| /trusted-firmware-a-3.7.0/plat/nuvoton/npcm845x/ |
| D | npcm845x_bl31_setup.c | 35 static entry_point_info_t bl33_image_ep_info; variable
70 ? &bl33_image_ep_info : &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
168 SET_PARAM_HEAD(&bl33_image_ep_info, in bl31_early_platform_setup2()
177 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); in bl31_early_platform_setup2()
179 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); in bl31_early_platform_setup2()
180 bl33_image_ep_info.spsr &= ~0x8; in bl31_early_platform_setup2()
181 bl33_image_ep_info.spsr |= 0x4; in bl31_early_platform_setup2()
183 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, (uint32_t)NON_SECURE); in bl31_early_platform_setup2()
190 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_DRAM1_BASE; in bl31_early_platform_setup2()
200 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; in bl31_early_platform_setup2()
[all …]
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| /trusted-firmware-a-3.7.0/plat/rpi/rpi3/ |
| D | rpi3_bl31_setup.c | 25 static entry_point_info_t bl33_image_ep_info; variable
40 ? &bl33_image_ep_info : &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
102 bl33_image_ep_info = *bl_params->ep_info; in bl31_early_platform_setup2()
108 if (bl33_image_ep_info.pc == 0) { in bl31_early_platform_setup2()
122 bl33_image_ep_info.args.arg0 = 0U; in bl31_early_platform_setup2()
123 bl33_image_ep_info.args.arg1 = ~0U; in bl31_early_platform_setup2()
124 bl33_image_ep_info.args.arg2 = (u_register_t) RPI3_PRELOADED_DTB_BASE; in bl31_early_platform_setup2()
133 bl33_image_ep_info.args.arg0 = (u_register_t) RPI3_PRELOADED_DTB_BASE; in bl31_early_platform_setup2()
134 bl33_image_ep_info.args.arg1 = 0ULL; in bl31_early_platform_setup2()
135 bl33_image_ep_info.args.arg2 = 0ULL; in bl31_early_platform_setup2()
[all …]
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| /trusted-firmware-a-3.7.0/plat/arm/common/sp_min/ |
| D | arm_sp_min_setup.c | 19 static entry_point_info_t bl33_image_ep_info; variable
49 next_image_info = &bl33_image_ep_info; in sp_min_plat_get_bl33_ep_info()
76 SET_PARAM_HEAD(&bl33_image_ep_info, in arm_sp_min_early_platform_setup()
84 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); in arm_sp_min_early_platform_setup()
85 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); in arm_sp_min_early_platform_setup()
86 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in arm_sp_min_early_platform_setup()
96 bl33_image_ep_info.args.arg0 = 0U; in arm_sp_min_early_platform_setup()
97 bl33_image_ep_info.args.arg1 = ~0U; in arm_sp_min_early_platform_setup()
98 bl33_image_ep_info.args.arg2 = (u_register_t)ARM_PRELOADED_DTB_BASE; in arm_sp_min_early_platform_setup()
119 bl33_image_ep_info = *bl_params->ep_info; in arm_sp_min_early_platform_setup()
[all …]
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| /trusted-firmware-a-3.7.0/plat/intel/soc/agilex5/ |
| D | bl31_plat_setup.c | 30 static entry_point_info_t bl33_image_ep_info; variable
42 &bl33_image_ep_info : &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
77 SET_PARAM_HEAD(&bl33_image_ep_info, in bl31_early_platform_setup2()
89 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; in bl31_early_platform_setup2()
90 bl33_image_ep_info.args.arg1 = 0U; in bl31_early_platform_setup2()
91 bl33_image_ep_info.args.arg2 = 0U; in bl31_early_platform_setup2()
92 bl33_image_ep_info.args.arg3 = 0U; in bl31_early_platform_setup2()
112 bl33_image_ep_info = *bl_params->ep_info; in bl31_early_platform_setup2()
124 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; in bl31_early_platform_setup2()
127 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; in bl31_early_platform_setup2()
[all …]
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| /trusted-firmware-a-3.7.0/plat/rpi/rpi4/ |
| D | rpi4_bl31_setup.c | 49 static entry_point_info_t bl33_image_ep_info; variable
64 ? &bl33_image_ep_info : &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
141 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); in bl31_early_platform_setup2()
142 bl33_image_ep_info.spsr = rpi3_get_spsr_for_bl33_entry(); in bl31_early_platform_setup2()
143 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in bl31_early_platform_setup2()
155 bl33_image_ep_info.args.arg0 = 0U; in bl31_early_platform_setup2()
156 bl33_image_ep_info.args.arg1 = ~0U; in bl31_early_platform_setup2()
157 bl33_image_ep_info.args.arg2 = rpi4_get_dtb_address(); in bl31_early_platform_setup2()
166 bl33_image_ep_info.args.arg0 = rpi4_get_dtb_address(); in bl31_early_platform_setup2()
167 bl33_image_ep_info.args.arg1 = 0ULL; in bl31_early_platform_setup2()
[all …]
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| /trusted-firmware-a-3.7.0/plat/qti/common/src/ |
| D | qti_bl31_setup.c | 29 static entry_point_info_t bl33_image_ep_info; variable
73 bl31_params_parse_helper(from_bl2, NULL, &bl33_image_ep_info); in bl31_early_platform_setup()
125 assert(bl33_image_ep_info.h.type == PARAM_EP); in bl31_plat_get_next_image_ep_info()
126 assert(bl33_image_ep_info.h.attr == NON_SECURE); in bl31_plat_get_next_image_ep_info()
131 if (bl33_image_ep_info.pc) { in bl31_plat_get_next_image_ep_info()
132 return &bl33_image_ep_info; in bl31_plat_get_next_image_ep_info()
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| /trusted-firmware-a-3.7.0/plat/hisilicon/poplar/ |
| D | bl31_plat_setup.c | 33 static entry_point_info_t bl33_image_ep_info; variable
47 ? &bl33_image_ep_info : &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
99 bl33_image_ep_info = *bl_params->ep_info; in bl31_early_platform_setup2()
104 if (bl33_image_ep_info.pc == 0) in bl31_early_platform_setup2()
136 bl33_image_ep_info.pc, bl33_image_ep_info.args.arg2); in bl31_plat_arch_setup()
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| /trusted-firmware-a-3.7.0/plat/imx/imx93/ |
| D | imx93_bl31_setup.c | 39 static entry_point_info_t bl33_image_ep_info; variable
73 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; in bl31_early_platform_setup2()
74 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); in bl31_early_platform_setup2()
75 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in bl31_early_platform_setup2()
85 bl33_image_ep_info.args.arg1 = BL32_BASE; in bl31_early_platform_setup2()
86 bl33_image_ep_info.args.arg2 = BL32_SIZE; in bl31_early_platform_setup2()
90 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; in bl31_early_platform_setup2()
147 return &bl33_image_ep_info; in bl31_plat_get_next_image_ep_info()
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| /trusted-firmware-a-3.7.0/plat/ti/k3/common/ |
| D | k3_bl31_setup.c | 44 static entry_point_info_t bl33_image_ep_info; variable
85 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); in bl31_early_platform_setup2()
86 bl33_image_ep_info.pc = PRELOADED_BL33_BASE; in bl31_early_platform_setup2()
87 bl33_image_ep_info.spsr = k3_get_spsr_for_bl33_entry(); in bl31_early_platform_setup2()
88 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in bl31_early_platform_setup2()
97 bl33_image_ep_info.args.arg0 = (u_register_t)K3_HW_CONFIG_BASE; in bl31_early_platform_setup2()
98 bl33_image_ep_info.args.arg1 = 0U; in bl31_early_platform_setup2()
99 bl33_image_ep_info.args.arg2 = 0U; in bl31_early_platform_setup2()
100 bl33_image_ep_info.args.arg3 = 0U; in bl31_early_platform_setup2()
181 next_image_info = (type == NON_SECURE) ? &bl33_image_ep_info : in bl31_plat_get_next_image_ep_info()
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| /trusted-firmware-a-3.7.0/plat/arm/common/ |
| D | arm_bl31_setup.c | 28 static entry_point_info_t bl33_image_ep_info; variable
89 next_image_info = &bl33_image_ep_info; in bl31_plat_get_next_image_ep_info()
153 SET_PARAM_HEAD(&bl33_image_ep_info, in arm_bl31_early_platform_setup()
161 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); in arm_bl31_early_platform_setup()
163 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); in arm_bl31_early_platform_setup()
164 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in arm_bl31_early_platform_setup()
226 bl33_image_ep_info = *bl_params->ep_info; in arm_bl31_early_platform_setup()
232 if (bl33_image_ep_info.pc == 0U) in arm_bl31_early_platform_setup()
252 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; in arm_bl31_early_platform_setup()
254 bl33_image_ep_info.args.arg0 = (u_register_t)hw_config; in arm_bl31_early_platform_setup()
[all …]
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| /trusted-firmware-a-3.7.0/plat/marvell/armada/common/ |
| D | marvell_bl31_setup.c | 28 static entry_point_info_t bl33_image_ep_info; variable
50 ? &bl33_image_ep_info : &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
89 SET_PARAM_HEAD(&bl33_image_ep_info, in marvell_bl31_early_platform_setup()
97 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); in marvell_bl31_early_platform_setup()
98 bl33_image_ep_info.spsr = marvell_get_spsr_for_bl33_entry(); in marvell_bl31_early_platform_setup()
99 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in marvell_bl31_early_platform_setup()
129 bl33_image_ep_info = *bl_params->ep_info; in marvell_bl31_early_platform_setup()
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| /trusted-firmware-a-3.7.0/plat/xilinx/zynqmp/ |
| D | bl31_zynqmp_setup.c | 30 static entry_point_info_t bl33_image_ep_info; variable
44 next_image_info = &bl33_image_ep_info; in bl31_plat_get_next_image_ep_info()
60 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); in bl31_set_default_config()
61 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, in bl31_set_default_config()
91 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); in bl31_early_platform_setup2()
92 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in bl31_early_platform_setup2()
101 &bl33_image_ep_info, in bl31_early_platform_setup2()
110 if (bl33_image_ep_info.pc != 0) { in bl31_early_platform_setup2()
111 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); in bl31_early_platform_setup2()
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| /trusted-firmware-a-3.7.0/plat/st/stm32mp1/sp_min/ |
| D | sp_min_setup.c | 35 static entry_point_info_t bl33_image_ep_info; variable
70 next_image_info = &bl33_image_ep_info; in sp_min_plat_get_bl33_ep_info()
142 bl33_image_ep_info = *bl_params->ep_info; in sp_min_early_platform_setup2()
148 bl33_image_ep_info.args.arg0 = 0U; in sp_min_early_platform_setup2()
149 bl33_image_ep_info.args.arg1 = 0U; in sp_min_early_platform_setup2()
150 bl33_image_ep_info.args.arg2 = arg2; in sp_min_early_platform_setup2()
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| /trusted-firmware-a-3.7.0/plat/allwinner/common/ |
| D | sunxi_bl31_setup.c | 31 static entry_point_info_t bl33_image_ep_info; variable
96 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); in bl31_early_platform_setup2()
101 bl33_image_ep_info.pc = PRELOADED_BL33_BASE; in bl31_early_platform_setup2()
102 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, in bl31_early_platform_setup2()
104 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in bl31_early_platform_setup2()
198 return &bl33_image_ep_info; in bl31_plat_get_next_image_ep_info()
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| /trusted-firmware-a-3.7.0/plat/socionext/uniphier/ |
| D | uniphier_bl31_setup.c | 22 static entry_point_info_t bl33_image_ep_info; variable
28 return type == NON_SECURE ? &bl33_image_ep_info : &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
51 bl33_image_ep_info = *bl_params->ep_info; in bl31_early_platform_setup2()
56 if (bl33_image_ep_info.pc == 0) in bl31_early_platform_setup2()
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| /trusted-firmware-a-3.7.0/plat/imx/imx8m/imx8mp/ |
| D | imx8mp_bl31_setup.c | 80 static entry_point_info_t bl33_image_ep_info; variable
158 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; in bl31_early_platform_setup2()
159 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); in bl31_early_platform_setup2()
160 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in bl31_early_platform_setup2()
170 bl33_image_ep_info.args.arg1 = BL32_BASE; in bl31_early_platform_setup2()
171 bl33_image_ep_info.args.arg2 = BL32_SIZE; in bl31_early_platform_setup2()
179 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; in bl31_early_platform_setup2()
239 return &bl33_image_ep_info; in bl31_plat_get_next_image_ep_info()
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| /trusted-firmware-a-3.7.0/plat/imx/imx8m/imx8mn/ |
| D | imx8mn_bl31_setup.c | 84 static entry_point_info_t bl33_image_ep_info; variable
169 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; in bl31_early_platform_setup2()
170 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); in bl31_early_platform_setup2()
171 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in bl31_early_platform_setup2()
181 bl33_image_ep_info.args.arg1 = BL32_BASE; in bl31_early_platform_setup2()
182 bl33_image_ep_info.args.arg2 = BL32_SIZE; in bl31_early_platform_setup2()
190 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; in bl31_early_platform_setup2()
250 return &bl33_image_ep_info; in bl31_plat_get_next_image_ep_info()
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| /trusted-firmware-a-3.7.0/plat/xilinx/versal_net/ |
| D | bl31_versal_net_setup.c | 30 static entry_point_info_t bl33_image_ep_info; variable
43 return &bl33_image_ep_info; in bl31_plat_get_next_image_ep_info()
56 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); in bl31_set_default_config()
57 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, in bl31_set_default_config()
114 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); in bl31_early_platform_setup2()
115 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in bl31_early_platform_setup2()
126 xbl_ret = xbl_handover(&bl32_image_ep_info, &bl33_image_ep_info, in bl31_early_platform_setup2()
157 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); in bl31_early_platform_setup2()
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| /trusted-firmware-a-3.7.0/plat/xilinx/versal/ |
| D | bl31_versal_setup.c | 30 static entry_point_info_t bl33_image_ep_info; variable
43 return &bl33_image_ep_info; in bl31_plat_get_next_image_ep_info()
56 bl33_image_ep_info.pc = (uintptr_t)plat_get_ns_image_entrypoint(); in bl31_set_default_config()
57 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX, in bl31_set_default_config()
93 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); in bl31_early_platform_setup2()
94 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in bl31_early_platform_setup2()
108 &bl33_image_ep_info, in bl31_early_platform_setup2()
134 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); in bl31_early_platform_setup2()
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| /trusted-firmware-a-3.7.0/plat/imx/imx8m/imx8mq/ |
| D | imx8mq_bl31_setup.c | 66 static entry_point_info_t bl33_image_ep_info; variable
168 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; in bl31_early_platform_setup2()
169 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); in bl31_early_platform_setup2()
170 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in bl31_early_platform_setup2()
180 bl33_image_ep_info.args.arg1 = BL32_BASE; in bl31_early_platform_setup2()
181 bl33_image_ep_info.args.arg2 = BL32_SIZE; in bl31_early_platform_setup2()
189 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; in bl31_early_platform_setup2()
239 return &bl33_image_ep_info; in bl31_plat_get_next_image_ep_info()
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| /trusted-firmware-a-3.7.0/plat/imx/imx8m/imx8mm/ |
| D | imx8mm_bl31_setup.c | 93 static entry_point_info_t bl33_image_ep_info; variable
165 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; in bl31_early_platform_setup2()
166 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); in bl31_early_platform_setup2()
167 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in bl31_early_platform_setup2()
177 bl33_image_ep_info.args.arg1 = BL32_BASE; in bl31_early_platform_setup2()
178 bl33_image_ep_info.args.arg2 = BL32_SIZE; in bl31_early_platform_setup2()
186 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; in bl31_early_platform_setup2()
246 return &bl33_image_ep_info; in bl31_plat_get_next_image_ep_info()
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| /trusted-firmware-a-3.7.0/plat/socionext/synquacer/ |
| D | sq_bl31_setup.c | 21 static entry_point_info_t bl33_image_ep_info; variable
44 return type == NON_SECURE ? &bl33_image_ep_info : &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
69 bl33_image_ep_info = *bl_params->ep_info; in bl31_early_platform_setup2()
149 SET_PARAM_HEAD(&bl33_image_ep_info, in bl31_early_platform_setup2()
157 bl33_image_ep_info.pc = PRELOADED_BL33_BASE; in bl31_early_platform_setup2()
158 bl33_image_ep_info.spsr = sq_get_spsr_for_bl33_entry(); in bl31_early_platform_setup2()
159 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in bl31_early_platform_setup2()
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| /trusted-firmware-a-3.7.0/plat/arm/board/arm_fpga/ |
| D | fpga_bl31_setup.c | 24 static entry_point_info_t bl33_image_ep_info; variable
58 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); in bl31_early_platform_setup2()
59 bl33_image_ep_info.spsr = fpga_get_spsr_for_bl33_entry(); in bl31_early_platform_setup2()
60 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in bl31_early_platform_setup2()
63 bl33_image_ep_info.args.arg0 = (u_register_t)FPGA_PRELOADED_DTB_BASE; in bl31_early_platform_setup2()
64 bl33_image_ep_info.args.arg1 = 0U; in bl31_early_platform_setup2()
65 bl33_image_ep_info.args.arg2 = 0U; in bl31_early_platform_setup2()
66 bl33_image_ep_info.args.arg3 = 0U; in bl31_early_platform_setup2()
111 next_image_info = &bl33_image_ep_info; in bl31_plat_get_next_image_ep_info()
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| /trusted-firmware-a-3.7.0/plat/qemu/common/ |
| D | qemu_bl31_setup.c | 42 static entry_point_info_t bl33_image_ep_info; variable
83 bl33_image_ep_info = *bl_params->ep_info; in bl31_early_platform_setup2()
88 if (!bl33_image_ep_info.pc) in bl31_early_platform_setup2()
139 ? &bl33_image_ep_info : &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
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