| /trusted-firmware-a-3.7.0/include/lib/ |
| D | mmio.h | 12 static inline void mmio_write_8(uintptr_t addr, uint8_t value) in mmio_write_8() argument
14 *(volatile uint8_t*)addr = value; in mmio_write_8()
17 static inline uint8_t mmio_read_8(uintptr_t addr) in mmio_read_8() argument
19 return *(volatile uint8_t*)addr; in mmio_read_8()
22 static inline void mmio_write_16(uintptr_t addr, uint16_t value) in mmio_write_16() argument
24 *(volatile uint16_t*)addr = value; in mmio_write_16()
27 static inline uint16_t mmio_read_16(uintptr_t addr) in mmio_read_16() argument
29 return *(volatile uint16_t*)addr; in mmio_read_16()
32 static inline void mmio_clrsetbits_16(uintptr_t addr, in mmio_clrsetbits_16() argument
36 mmio_write_16(addr, (mmio_read_16(addr) & ~clear) | set); in mmio_clrsetbits_16()
[all …]
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| /trusted-firmware-a-3.7.0/common/backtrace/ |
| D | backtrace.c | 65 uintptr_t addr = extract_address(address); in is_address_readable() local
68 ats1e3r(addr); in is_address_readable()
70 ats1e2r(addr); in is_address_readable()
72 AT(ats1e1r, addr); in is_address_readable()
84 static bool is_address_readable(uintptr_t addr) in is_address_readable() argument
89 write_ats1cpr(addr); in is_address_readable()
91 write_ats1hr(addr); in is_address_readable()
93 write_ats1cpr(addr); in is_address_readable()
110 static bool is_valid_object(uintptr_t addr, size_t size) in is_valid_object() argument
114 if (addr == 0U) in is_valid_object()
[all …]
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| /trusted-firmware-a-3.7.0/plat/marvell/armada/common/mss/ |
| D | mss_ipc_drv.c | 54 unsigned int addr; in mv_pm_ipc_queue_addr_get() local
61 addr = (unsigned int)(mv_pm_ipc_msg_base + in mv_pm_ipc_queue_addr_get()
66 return addr; in mv_pm_ipc_queue_addr_get()
77 unsigned int addr = mv_pm_ipc_queue_addr_get(); in mv_pm_ipc_msg_rx() local
79 msg->msg_reply = mmio_read_32(addr + IPC_MSG_REPLY_LOC); in mv_pm_ipc_msg_rx()
93 unsigned int addr = mv_pm_ipc_queue_addr_get(); in mv_pm_ipc_msg_tx() local
96 if (mmio_read_32(addr + IPC_MSG_STATE_LOC) == IPC_MSG_FREE) { in mv_pm_ipc_msg_tx()
101 mmio_write_32(addr + IPC_MSG_SYNC_ID_LOC, msg_sync); in mv_pm_ipc_msg_tx()
102 mmio_write_32(addr + IPC_MSG_ID_LOC, msg_id); in mv_pm_ipc_msg_tx()
103 mmio_write_32(addr + IPC_MSG_CPU_ID_LOC, channel_id); in mv_pm_ipc_msg_tx()
[all …]
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| /trusted-firmware-a-3.7.0/include/drivers/arm/css/ |
| D | css_mhu_doorbell.h | 26 #define MHU_RING_DOORBELL(addr, modify_mask, preserve_mask) do { \ argument
27 uint32_t db = mmio_read_32(addr) & (preserve_mask); \
28 mmio_write_32(addr, db | (modify_mask)); \
31 #define MHU_V2_ACCESS_REQUEST(addr) \ argument
32 mmio_write_32((addr) + MHU_V2_ACCESS_REQ_OFFSET, 0x1)
34 #define MHU_V2_CLEAR_REQUEST(addr) \ argument
35 mmio_write_32((addr) + MHU_V2_ACCESS_REQ_OFFSET, 0x0)
37 #define MHU_V2_IS_ACCESS_READY(addr) \ argument
38 (mmio_read_32((addr) + MHU_V2_ACCESS_READY_OFFSET) & 0x1)
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| /trusted-firmware-a-3.7.0/include/drivers/nxp/crypto/caam/ |
| D | caam_io.h | 28 #define sec_in64(addr) ( \ argument
29 ((uint64_t)sec_in32((uintptr_t)(addr)) << 32) | \
30 (sec_in32(((uintptr_t)(addr)) + 4)))
31 #define sec_out64(addr, val) ({ \ argument
32 sec_out32(((uintptr_t)(addr)), (uint32_t)((val) >> 32)); \
33 sec_out32(((uintptr_t)(addr)) + 4, (uint32_t)(val)); })
37 #define sec_in64(addr) ( \ argument
38 ((uint64_t)sec_in32((uintptr_t)(addr) + 4) << 32) | \
39 (sec_in32((uintptr_t)(addr))))
40 #define sec_out64(addr, val) ({ \ argument
[all …]
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| /trusted-firmware-a-3.7.0/plat/rockchip/rk3399/drivers/m0/include/ |
| D | rk3399_mcu.h | 18 #define mmio_clrbits_32(addr, clear) \ argument
19 mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)))
20 #define mmio_setbits_32(addr, set) \ argument
21 mmio_write_32(addr, (mmio_read_32(addr)) | (set))
22 #define mmio_clrsetbits_32(addr, clear, set) \ argument
23 mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)) | (set))
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| /trusted-firmware-a-3.7.0/drivers/marvell/secure_dfx_access/ |
| D | misc_dfx.c | 57 static _Bool is_valid(u_register_t addr) in is_valid() argument
59 switch (addr) { in is_valid()
83 static int armada_dfx_sread(u_register_t *read, u_register_t addr) in armada_dfx_sread() argument
85 if (!is_valid(addr)) in armada_dfx_sread()
88 *read = mmio_read_32(addr); in armada_dfx_sread()
93 static int armada_dfx_swrite(u_register_t addr, u_register_t val) in armada_dfx_swrite() argument
95 if (!is_valid(addr)) in armada_dfx_swrite()
98 mmio_write_32(addr, val); in armada_dfx_swrite()
104 u_register_t addr, u_register_t val) in mvebu_dfx_misc_handle() argument
108 debug("func %ld, addr 0x%lx, val 0x%lx\n", func, addr, val); in mvebu_dfx_misc_handle()
[all …]
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| /trusted-firmware-a-3.7.0/plat/brcm/board/stingray/driver/ |
| D | swreg.c | 158 static int write_swreg_config(enum sw_reg reg_id, uint32_t addr, uint32_t data) in write_swreg_config() argument
163 cmd = BSTI_CMD(0x1, BSTI_WRITE, reg_id, addr, BSTI_COMMAND_TA, data); in write_swreg_config()
169 sw_reg_name[reg_id-1], addr); in write_swreg_config()
175 static int read_swreg_config(enum sw_reg reg_id, uint32_t addr, uint32_t *data) in read_swreg_config() argument
180 cmd = BSTI_CMD(0x1, BSTI_READ, reg_id, addr, BSTI_COMMAND_TA, PHY_REG0); in read_swreg_config()
186 sw_reg_name[reg_id-1], addr); in read_swreg_config()
227 int addr; in dump_swreg_firmware() local
232 for (addr = MIN_REG_ADDR; addr <= MAX_REG_ADDR; addr++) { in dump_swreg_firmware()
233 ret = read_swreg_config(reg_id, addr, &data); in dump_swreg_firmware()
235 ERROR("Failed to read offset %d\n", addr); in dump_swreg_firmware()
[all …]
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| /trusted-firmware-a-3.7.0/plat/qti/common/src/ |
| D | spmi_arb.c | 35 static int addr_to_apid(uint32_t addr) in addr_to_apid() argument
41 if ((reg != 0U) && ((addr & PPID_MASK) == (reg & PPID_MASK))) { in addr_to_apid()
69 static void arb_command(uint16_t apid, uint8_t opcode, uint32_t addr, in arb_command() argument
73 (addr & 0xff) << 4 | (bytes - 1)); in arb_command()
76 int spmi_arb_read8(uint32_t addr) in spmi_arb_read8() argument
78 int apid = addr_to_apid(addr); in spmi_arb_read8()
84 arb_command(apid, OPC_EXT_READL, addr, 1); in spmi_arb_read8()
88 ERROR("SPMI_ARB read error [0x%x]: 0x%x\n", addr, ret); in spmi_arb_read8()
95 int spmi_arb_write8(uint32_t addr, uint8_t data) in spmi_arb_write8() argument
97 int apid = addr_to_apid(addr); in spmi_arb_write8()
[all …]
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| /trusted-firmware-a-3.7.0/drivers/renesas/rcar/cpld/ |
| D | ulcb_cpld.c | 34 static void gpio_set_value(uint32_t addr, uint8_t gpio, uint32_t val) in gpio_set_value() argument
38 reg = mmio_read_32(addr); in gpio_set_value()
43 mmio_write_32(addr, reg); in gpio_set_value()
46 static void gpio_direction_output(uint32_t addr, uint8_t gpio) in gpio_direction_output() argument
50 reg = mmio_read_32(addr); in gpio_direction_output()
52 mmio_write_32(addr, reg); in gpio_direction_output()
55 static void gpio_pfc(uint32_t addr, uint8_t gpio) in gpio_pfc() argument
59 reg = mmio_read_32(addr); in gpio_pfc()
62 mmio_write_32(addr, reg); in gpio_pfc()
65 static void cpld_write(uint8_t addr, uint32_t data) in cpld_write() argument
[all …]
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| /trusted-firmware-a-3.7.0/plat/nxp/common/setup/ |
| D | ls_common.c | 67 (void *) info_dram_regions->region[i].addr, in mmap_add_ddr_regions_statically()
68 (void *) (info_dram_regions->region[i].addr in mmap_add_ddr_regions_statically()
71 mmap_add_region(info_dram_regions->region[i].addr, in mmap_add_ddr_regions_statically()
72 info_dram_regions->region[i].addr, in mmap_add_ddr_regions_statically()
80 (void *) (info_dram_regions->region[i].addr in mmap_add_ddr_regions_statically()
82 (void *) (info_dram_regions->region[i].addr in mmap_add_ddr_regions_statically()
87 mmap_add_region((info_dram_regions->region[i].addr in mmap_add_ddr_regions_statically()
89 (info_dram_regions->region[i].addr in mmap_add_ddr_regions_statically()
100 (void *) info_dram_regions->region[i].addr, in mmap_add_ddr_regions_statically()
101 (void *) (info_dram_regions->region[i].addr in mmap_add_ddr_regions_statically()
[all …]
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| /trusted-firmware-a-3.7.0/include/drivers/brcm/ |
| D | chimp.h | 45 void bcm_chimp_write(uintptr_t addr, uint32_t value);
46 uint32_t bcm_chimp_read(uintptr_t addr);
48 void bcm_chimp_clrbits(uintptr_t addr, uint32_t bits);
49 void bcm_chimp_setbits(uintptr_t addr, uint32_t bits);
57 static inline void bcm_chimp_write(uintptr_t addr, uint32_t value) in bcm_chimp_write() argument
60 static inline uint32_t bcm_chimp_read(uintptr_t addr) in bcm_chimp_read() argument
68 static inline void bcm_chimp_clrbits(uintptr_t addr, uint32_t bits) in bcm_chimp_clrbits() argument
71 static inline void bcm_chimp_setbits(uintptr_t addr, uint32_t bits) in bcm_chimp_setbits() argument
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| /trusted-firmware-a-3.7.0/plat/arm/board/corstone700/common/drivers/mhu/ |
| D | corstone700_mhu.h | 21 #define MHU_V2_ACCESS_REQUEST(addr) \ argument
22 mmio_write_32((addr) + MHU_V2_ACCESS_REQ_OFFSET, 0x1)
24 #define MHU_V2_CLEAR_REQUEST(addr) \ argument
25 mmio_write_32((addr) + MHU_V2_ACCESS_REQ_OFFSET, 0x0)
27 #define MHU_V2_IS_ACCESS_READY(addr) \ argument
28 (mmio_read_32((addr) + MHU_V2_ACCESS_READY_OFFSET) & 0x1)
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| /trusted-firmware-a-3.7.0/drivers/marvell/comphy/ |
| D | phy-comphy-common.h | 124 static inline uint32_t polling_with_timeout(uintptr_t addr, uint32_t val, in polling_with_timeout() argument
134 data = mmio_read_16(addr) & mask; in polling_with_timeout()
136 data = mmio_read_32(addr) & mask; in polling_with_timeout()
145 static inline void reg_set(uintptr_t addr, uint32_t data, uint32_t mask) in reg_set() argument
148 addr, data, mask); in reg_set()
149 debug("old value = 0x%x ==> ", mmio_read_32(addr)); in reg_set()
150 mmio_clrsetbits_32(addr, mask, data & mask); in reg_set()
152 debug("new val 0x%x\n", mmio_read_32(addr)); in reg_set()
155 static inline void __unused reg_set16(uintptr_t addr, uint16_t data, in reg_set16() argument
160 addr, data, mask); in reg_set16()
[all …]
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| /trusted-firmware-a-3.7.0/drivers/brcm/ |
| D | chimp.c | 19 #define CHIMP_PREPARE_ACCESS_WINDOW(addr) \ argument
23 addr & 0xffc00000)\
25 #define CHIMP_INDIRECT_TGT_ADDR(addr) \ argument
26 (CHIMP_INDIRECT_BASE + (addr & CHIMP_INDIRECT_ADDR_MASK))
37 void bcm_chimp_write(uintptr_t addr, uint32_t value) in bcm_chimp_write() argument
39 CHIMP_PREPARE_ACCESS_WINDOW(addr); in bcm_chimp_write()
40 mmio_write_32(CHIMP_INDIRECT_TGT_ADDR(addr), value); in bcm_chimp_write()
43 uint32_t bcm_chimp_read(uintptr_t addr) in bcm_chimp_read() argument
45 CHIMP_PREPARE_ACCESS_WINDOW(addr); in bcm_chimp_read()
46 return mmio_read_32(CHIMP_INDIRECT_TGT_ADDR(addr)); in bcm_chimp_read()
[all …]
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| /trusted-firmware-a-3.7.0/plat/mediatek/drivers/ptp3/ |
| D | ptp3_common.c | 17 unsigned int i, addr, value; in ptp3_init() local
29 addr = ptp3_cfg2[i][PTP3_CFG_ADDR] + PTP3_CORE_OFT(core); in ptp3_init()
32 mmio_write_32(addr, value); in ptp3_init()
36 addr = ptp3_cfg2[i][PTP3_CFG_ADDR] + PTP3_CORE_OFT(core); in ptp3_init()
43 mmio_write_32(addr, value); in ptp3_init()
48 addr = ptp3_cfg3[PTP3_CFG_ADDR] + PTP3_CORE_OFT(core); in ptp3_init()
51 addr = ptp3_cfg3_ext[PTP3_CFG_ADDR] + PTP3_CORE_OFT(core); in ptp3_init()
54 mmio_write_32(addr, value & PTP3_CFG3_MASK1); in ptp3_init()
55 mmio_write_32(addr, value & PTP3_CFG3_MASK2); in ptp3_init()
56 mmio_write_32(addr, value & PTP3_CFG3_MASK3); in ptp3_init()
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| /trusted-firmware-a-3.7.0/plat/imx/common/ |
| D | imx_clock.c | 19 uintptr_t addr; in imx_clock_target_set() local
24 addr = (uintptr_t)&ccm->ccm_root_ctrl[id].ccm_target_root; in imx_clock_target_set()
25 mmio_write_32(addr, val); in imx_clock_target_set()
31 uintptr_t addr; in imx_clock_target_clr() local
36 addr = (uintptr_t)&ccm->ccm_root_ctrl[id].ccm_target_root_clr; in imx_clock_target_clr()
37 mmio_write_32(addr, val); in imx_clock_target_clr()
43 uintptr_t addr; in imx_clock_gate_enable() local
50 addr = (uintptr_t)&ccm->ccm_clk_gate_ctrl[id].ccm_ccgr_set; in imx_clock_gate_enable()
52 addr = (uintptr_t)&ccm->ccm_clk_gate_ctrl[id].ccm_ccgr_clr; in imx_clock_gate_enable()
54 mmio_write_32(addr, CCM_CCGR_SETTING0_DOM_CLK_ALWAYS); in imx_clock_gate_enable()
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| D | imx_aips.c | 16 uintptr_t addr; in imx_aips_set_default_access() local
27 addr = (uintptr_t)&aips_regs->aipstz_mpr; in imx_aips_set_default_access()
28 mmio_write_32(addr, 0x77777777); in imx_aips_set_default_access()
41 addr = (uintptr_t)&aips_regs->aipstz_opacr[i]; in imx_aips_set_default_access()
42 mmio_write_32(addr, 0x00000000); in imx_aips_set_default_access()
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| D | imx_snvs.c | 15 uintptr_t addr; in imx_snvs_init() local
18 addr = (uintptr_t)&snvs->hpcomr; in imx_snvs_init()
19 val = mmio_read_32(addr); in imx_snvs_init()
21 mmio_write_32(addr, val); in imx_snvs_init()
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| D | imx_io_mux.c | 14 uintptr_t addr = (uintptr_t)(MXC_IO_MUXC_BASE + pad_mux_offset); in imx_io_muxc_set_pad_alt_function() local
16 mmio_write_32(addr, alt_function); in imx_io_muxc_set_pad_alt_function()
21 uintptr_t addr = (uintptr_t)(MXC_IO_MUXC_BASE + pad_feature_offset); in imx_io_muxc_set_pad_features() local
23 mmio_write_32(addr, pad_features); in imx_io_muxc_set_pad_features()
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| /trusted-firmware-a-3.7.0/drivers/marvell/ |
| D | cache_llc.c | 160 uintptr_t addr, end_addr; in llc_sram_test() local
167 for (addr = PLAT_MARVELL_TRUSTED_RAM_BASE, in llc_sram_test()
169 addr < end_addr; addr += 4) { in llc_sram_test()
170 mmio_write_32(addr, addr); in llc_sram_test()
174 for (addr = PLAT_MARVELL_TRUSTED_RAM_BASE, in llc_sram_test()
176 addr < end_addr; addr += 4) { in llc_sram_test()
177 data = mmio_read_32(addr); in llc_sram_test()
178 if (data != addr) { in llc_sram_test()
180 msg, addr); in llc_sram_test()
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| /trusted-firmware-a-3.7.0/drivers/rpi3/mailbox/ |
| D | rpi3_mbox.c | 25 uintptr_t resp_addr, addr; in rpi3_vc_mailbox_request_send() local
29 addr = (uintptr_t)req; in rpi3_vc_mailbox_request_send()
32 flush_dcache_range(addr, req_size); in rpi3_vc_mailbox_request_send()
50 RPI3_CHANNEL_ARM_TO_VC | (uint32_t) addr); in rpi3_vc_mailbox_request_send()
75 if (addr != resp_addr) { in rpi3_vc_mailbox_request_send()
81 inv_dcache_range(addr, req_size); in rpi3_vc_mailbox_request_send()
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| /trusted-firmware-a-3.7.0/plat/mediatek/mt8186/drivers/spm/ |
| D | mt_spm_pmic_wrap.c | 29 struct pmic_wrap_cmd addr[NR_PMIC_WRAP_CMD]; member
51 .addr = { {0UL, 0UL} },
71 .addr = { {0UL, 0UL} },
108 memcpy(pw->addr, pwrap_cmd_default, sizeof(pwrap_cmd_default)); in _mt_spm_pmic_table_init()
113 uint32_t idx, addr, data; in mt_spm_pmic_wrap_set_phase() local
116 if (pw == NULL || pw->addr[0].cmd_addr == 0) { in mt_spm_pmic_wrap_set_phase()
126 addr = pw->set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
128 mmio_write_32(pw->addr[idx].cmd_addr, addr | data); in mt_spm_pmic_wrap_set_phase()
137 uint32_t addr; in mt_spm_pmic_wrap_set_cmd() local
151 addr = pw->set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
[all …]
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| /trusted-firmware-a-3.7.0/drivers/nxp/ddr/phy-gen2/ |
| D | phy.c | 37 static uint32_t map_phy_addr_space(uint32_t addr) in map_phy_addr_space() argument
40 uint32_t pstate = (addr & U(0x700000)) >> 20U; /* bit 22:20 */ in map_phy_addr_space()
41 uint32_t block_type = (addr & U(0x0f0000)) >> 16U; /* bit 19:16 */ in map_phy_addr_space()
42 uint32_t instance = (addr & U(0x00f000)) >> 12U; /* bit 15:12 */ in map_phy_addr_space()
43 uint32_t offset = (addr & U(0x000fff)); /* bit 11:0 */ in map_phy_addr_space()
70 static inline uint16_t *phy_io_addr(void *phy, uint32_t addr) in phy_io_addr() argument
72 return phy + (map_phy_addr_space(addr) << 2); in phy_io_addr()
75 static inline void phy_io_write16(uint16_t *phy, uint32_t addr, uint16_t data) in phy_io_write16() argument
77 mmio_write_16((uintptr_t)phy_io_addr(phy, addr), data); in phy_io_write16()
79 printf("0x%06x,0x%x\n", addr, data); in phy_io_write16()
[all …]
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| /trusted-firmware-a-3.7.0/plat/mediatek/mt8192/drivers/ptp3/ |
| D | mtk_ptp3_common.h | 16 #define ptp3_read(addr) mmio_read_32((uintptr_t)addr) argument
17 #define ptp3_write(addr, val) mmio_write_32((uintptr_t)addr, val) argument
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