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Searched refs:TEGRA_HSP_DBELL_BASE (Results 1 – 5 of 5) sorted by relevance

/trusted-firmware-a-3.7.0/plat/nvidia/tegra/drivers/bpmp_ipc/
Dintf.c40 return mmio_read_32((uint32_t)(TEGRA_HSP_DBELL_BASE + reg)); in hsp_db_read()
45 mmio_write_32((uint32_t)(TEGRA_HSP_DBELL_BASE + reg), val); in hsp_db_write()
/trusted-firmware-a-3.7.0/plat/nvidia/tegra/include/t186/
Dtegra_def.h231 #define TEGRA_HSP_DBELL_BASE U(0x03C90000) macro
/trusted-firmware-a-3.7.0/plat/nvidia/tegra/include/t194/
Dtegra_def.h193 #define TEGRA_HSP_DBELL_BASE U(0x03C90000) macro
/trusted-firmware-a-3.7.0/plat/nvidia/tegra/soc/t186/
Dplat_setup.c111 MAP_REGION_FLAT(TEGRA_HSP_DBELL_BASE, 0x10000U, /* 64KB */
/trusted-firmware-a-3.7.0/plat/nvidia/tegra/soc/t194/
Dplat_setup.c117 MAP_REGION_FLAT(TEGRA_HSP_DBELL_BASE, 0x1000U, /* 4KB */