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Searched refs:SUNXI_CCU_BASE (Results 1 – 10 of 10) sorted by relevance

/trusted-firmware-a-3.7.0/plat/allwinner/sun50i_a64/
Dsunxi_power.c46 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, ~BIT_32(14)); in sunxi_turn_off_soc()
47 mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, ~BIT_32(14)); in sunxi_turn_off_soc()
49 mmio_write_32(SUNXI_CCU_BASE + 0x2c4, 0); in sunxi_turn_off_soc()
50 mmio_write_32(SUNXI_CCU_BASE + 0x64, 0); in sunxi_turn_off_soc()
51 mmio_write_32(SUNXI_CCU_BASE + 0x2c8, 0); in sunxi_turn_off_soc()
53 mmio_clrbits_32(SUNXI_CCU_BASE + 0x68, ~(BIT_32(5))); in sunxi_turn_off_soc()
54 mmio_write_32(SUNXI_CCU_BASE + 0x2d0, 0); in sunxi_turn_off_soc()
56 mmio_write_32(SUNXI_CCU_BASE + 0x2d8, 0); in sunxi_turn_off_soc()
57 mmio_write_32(SUNXI_CCU_BASE + 0x6c, 0); in sunxi_turn_off_soc()
58 mmio_write_32(SUNXI_CCU_BASE + 0x70, 0); in sunxi_turn_off_soc()
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/trusted-firmware-a-3.7.0/plat/allwinner/sun50i_a64/include/
Dsunxi_ccu.h10 #define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0x02f0)
Dsunxi_mmap.h39 #define SUNXI_CCU_BASE 0x01c20000 macro
/trusted-firmware-a-3.7.0/plat/allwinner/sun50i_h6/include/
Dsunxi_ccu.h10 #define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0x0f00)
Dsunxi_mmap.h33 #define SUNXI_CCU_BASE 0x03001000 macro
/trusted-firmware-a-3.7.0/plat/allwinner/sun50i_h616/include/
Dsunxi_ccu.h10 #define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0x0f00)
Dsunxi_mmap.h26 #define SUNXI_CCU_BASE 0x03001000 macro
/trusted-firmware-a-3.7.0/plat/allwinner/sun50i_r329/include/
Dsunxi_ccu.h10 #define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0x0f00)
Dsunxi_mmap.h39 #define SUNXI_CCU_BASE 0x02001000 macro
/trusted-firmware-a-3.7.0/plat/allwinner/common/
Dsunxi_bl31_setup.c169 mmio_write_32(SUNXI_CCU_BASE + 0x54, 0x00003180); in bl31_platform_setup()
178 mmio_write_32(SUNXI_CCU_BASE + 0x5c, 0x1); in bl31_platform_setup()