Searched refs:SDCR (Results 1 – 7 of 7) sorted by relevance
| /trusted-firmware-a-3.7.0/include/arch/aarch32/ |
| D | smccc_macros.S | 95 ldcopr r5, SDCR
154 ldcopr r1, SDCR
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| D | el3_common_macros.S | 150 stcopr r0, SDCR
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| D | arch_helpers.h | 291 DEFINE_COPROCR_RW_FUNCS(sdcr, SDCR) in DEFINE_SYSREG_RW_FUNCS()
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| D | arch.h | 533 #define SDCR p15, 0, c1, c3, 1 macro
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| /trusted-firmware-a-3.7.0/docs/security_advisories/ |
| D | security-advisory-tfv-2.rst | 54 macro. Here the affected bits are ``SDCR.SPD``, which should also be assigned to
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| /trusted-firmware-a-3.7.0/docs/process/ |
| D | security-hardening.rst | 117 In Aarch32 execution state the ``MDCR_EL3`` alias is the ``SDCR`` register,
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| /trusted-firmware-a-3.7.0/docs/ |
| D | change-log.md | 6888 the counter gets disabled by setting `SDCR.SCCD` bit on CPU cold/warm
8050 - Debug registers MDCR-EL3/SDCR and MDCR_EL2/HDCR are initialised to avoid
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