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Searched refs:RTX_RESET_CTL0 (Results 1 – 2 of 2) sorted by relevance

/trusted-firmware-a-3.7.0/plat/imx/imx8m/imx8mp/
Dgpc.c198 mmio_write_32(IMX_HDMI_CTL_BASE + RTX_RESET_CTL0, 0x0); in imx_gpc_pm_domain_enable()
222 mmio_write_32(IMX_HDMI_CTL_BASE + RTX_RESET_CTL0, 0xffffffff); in imx_gpc_pm_domain_enable()
/trusted-firmware-a-3.7.0/plat/imx/imx8m/imx8mp/include/
Dplatform_def.h130 #define RTX_RESET_CTL0 U(0x20) macro